A semiconductor device, having a substrate including an insulating plate and a circuit board provided on a front surface of the insulating plate. The circuit board has a first disposition area and a second disposition area with a gap therebetween, and a groove portion, of which a longitudinal direction is parallel to the gap, formed in the gap. The semiconductor device further includes a first semiconductor chip and a second semiconductor chip located on the circuit board in the first disposition area and the second disposition area, respectively, and a blocking member located in the gap across the groove portion in parallel to the longitudinal direction in a plan view of the semiconductor device.

A flexible circuit board according to an embodiment of the present invention comprises: a substrate; a first wiring pattern layer disposed on a first surface of the substrate; a second wiring pattern layer disposed on a second surface opposite the first surface of the substrate; a first dummy pattern part disposed on the second surface of the substrate on which the second wiring pattern layer is not disposed; a first protection layer disposed on the first wiring pattern layer; and a second protection layer disposed on the second wiring pattern layer and the first dummy pattern part, wherein at least a part of the first dummy pattern part overlaps with the first wiring pattern layer in a vertical direction.

A circuit board includes a board, first connection pads disposed on the board and arranged in a first direction, second connection pads disposed on the board and arranged in the first direction, a driving chip disposed on the board and between the first connection pads and the second connection pads, and a first adhesive layer disposed on the board and overlapping with an entirety of the first connection pads in a plan view. The second connection pads are spaced apart from the first connection pads in a second direction perpendicular to the first direction.

A semiconductor package has a substrate, a chip and an encapsulation. The substrate has a dielectric layer, a copper wiring layer and a solder resist layer formed thereon. The copper wiring layer is formed on the dielectric layer and is covered by the solder resist layer. The solder resist layer has a chip area defined thereon and an annular opening formed thereon. The annular opening surrounds the chip area and exposes part of the copper wiring layer. The chip is mounted on the chip area and is encapsulated by the encapsulation. Therefore, the semiconductor package with the annular opening makes the solder resist layer discontinuous, and the concentration stress is decreased to avoid a crack formed on the solder resist layer or the copper wiring layer when doing thermal-cycle test.

An electrical component is provided by metallizing holes that extend through a glass substrate. The electrical component can be fabricated by forcing a suspension of electrically conductive particles suspended in a liquid medium through the holes. The suspension can be forced into the holes under an air pressure differential such as a pressure differential force, a centrifugal force, or an electrostatic force. The liquid medium in the holes can be dried, and the particles can be sintered. The particles can further be packed in the hole. Alternatively or additionally, the particles can be pressed against the outer surfaces of the substrate to produce buttons.

Embodiments described herein may be related to apparatuses, processes, and techniques related to glass interposers or substrates that may be created using a glass etching process to enable highly integrated modules. Planar structures, which may be vertical planar structures, created within the glass interposer may be used to provide shielding for conductive vias in the glass interposer, to increase the signal density within the glass substrate and to reduce cross talk. Other embodiments may be described and/or claimed.

A bonding pad such as for a ball grid array includes a conductive pad having a top surface and a first interface surface in contact with a signal trace of a substrate, and a plating layer having a bottom surface in direct contact with the top surface of the conductive pad. The plating layer includes one or more protrusions extending toward the signal trace in a direction generally parallel to a longitudinal axis of the signal trace. Each of the one or more protrusions includes two parallel sidewalls extending upwardly from the bottom surface of the plating layer, and a second interface surface contiguous with the bottom surface of the plating layer. The second interface surface is positioned over and in direct contact with a top surface of the signal trace. The protrusions prevent the connection to the signal trace from being compromised.

Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.

Embodiments include forming a die, the die including a pad and a passivation layer over the pad. A via is formed to the pad through the passivation layer. A solder cap is formed on the via, where a first material of the solder cap flows to the sidewall of the via. In some embodiments, the via is encapsulated in a first encapsulant, where the first encapsulant is a polymer or molding compound selected to have a low co-efficient of thermal expansion and/or low curing temperature. In some embodiments, the first material of the solder cap is removed from the sidewall of the via by an etching process and the via is encapsulated in a first encapsulant.

A power module is provided with reduced power and gate loop inductance. The power module may be configured in a multi-layer manner with one or more organic substrates.