A fuse structure includes a fusing line including a first portion, a second portion, and a central portion between the first portion and the second portion; and a dummy fuse neighboring the fusing line, the dummy fuse may include: a first air dummy fuse including a plurality of first air gaps extending in a first direction parallel to the fusing line; and a second air dummy fuse including a second air gap extending in a second direction crossing the fusing line.

A method for integrating vertical transistors and electric fuses includes forming fins through a dielectric layer and a dummy gate stack on a substrate; thinning top portions of the fins by an etch process; epitaxially growing top source/drain regions on thinned portions of the fins in a transistor region and top cathode/anode regions on the thinned portions of the fins in a fuse region; and removing the dummy gate layer and exposing sidewalls of the fins. The fuse region is blocked to form a gate structure in the transistor region. The transistor region is blocked and the fuse region is exposed to conformally deposit a metal on exposed sidewalls of the fins. The metal is annealed to form silicided fins. Portions of the substrate are separated to form bottom source/drain regions for vertical transistors in the transistor region and bottom cathode/anode regions for fuses in the fuse region.

A fuse memory comprising a discharge circuit is provided. The fuse memory includes a fuse cell array comprising fuse cells connected to read word lines, programs word lines, and bit lines arranged in rows and columns; and at least one discharge circuit arranged in each of the rows. The discharge circuit discharges a voltage level of a program word line of the fuse cells selected in a read mode to a ground voltage.

Provided is a semiconductor device preventing readhesion of conductive body which forms fuse elements and breakage of the fuse elements. The semiconductor device includes a first insulating film formed on a semiconductor substrate, a plurality of fuse elements formed on the first insulating film adjacent to one another, a protective insulating film covering at least side surfaces of the fuse elements, and a second insulating film formed of one of a BPSG film and a PSG film to cover the fuse elements and the protective insulating film. The protective insulating film is higher in mechanical strength than the second insulating film.

A semiconductor device includes a stack of layers stacked vertically and including a source layer, a drain layer and a channel layer between the source layer and the drain layer. A gate electrode is formed in a common plane with the channel layer and a gate dielectric is formed vertically between the gate electrode and the channel layer. A first contact contacts the stack of layers on a first side of the stack of layers, and a second contact formed on an opposite side vertically from the first contact.

A structure of an e-Fuse device in a semiconductor device is described. The e-Fuse device includes an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions. The anode and cathode regions are comprised of a large grained copper layer and an aspect ratio reducing layer, and the fuse element is comprised of a fine grained copper structure.

A structure for an e-Fuse device in a semiconductor device is described. The e-Fuse device includes an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions. The anode and cathode regions are comprised of a high EM-resistant conductive material. The fuse element is comprised of low EM-resistant conductive material.

A non-volatile nanotube switch and memory arrays constructed from these switches are disclosed. A non-volatile nanotube switch includes a conductive terminal and a nanoscopic element stack having a plurality of nanoscopic elements arranged in direct electrical contact, a first comprising a nanotube fabric and a second comprising a carbon material, a portion of the nanoscopic element stack in electrical contact with the conductive terminal. Control circuitry is provided in electrical communication with and for applying electrical stimulus to the conductive terminal and to at least a portion of the nanoscopic element stack. At least one of the nanoscopic elements is capable of switching among a plurality of electronic states in response to a corresponding electrical stimuli applied by the control circuitry to the conductive terminal and the portion of the nanoscopic element stack. For each electronic state, the nanoscopic element stack provides an electrical pathway of corresponding resistance.

A fuse structure is provided above a first portion of a semiconductor material. The fuse structure includes a first end region containing a first portion of a metal structure having a first thickness, a second end region containing a second portion of the metal structure having the first thickness, and a neck region located between the first and second end regions. The neck region contains a third portion of the metal structure having a second thickness that is less than the first thickness, wherein a portion of the neck region is located in a gap positioned between a bottom III-V compound semiconductor material portion and a top III-V compound semiconductor material portion.

Provided is a semiconductor device applicable to both types of packages regardless of whether or not double bonding of a lead frame pad is allowed. The semiconductor device includes: an operational amplifier; a feedback resistor; a reference voltage generation circuit; an output transistor; a first pad which is connected to an output terminal of the output transistor, and is to be selectively connected to a lead frame pad by a bonding wire; a second pad to be selectively connected to the lead frame pad by a bonding wire; and a connection switching element provided between the first pad and the second pad. In a case in which the second pad is connected to the lead frame pad by the bonding wire, the connection switching element interrupts connection between the first pad and the second pad.