A semiconductor device includes an electrical circuit having a first set of circuit elements, wherein the electrical circuit is in a circuit area on a first side of a substrate, and a first set of conductive pillars over the first side of the substrate. In the semiconductor device, a first conductive rail electrically connects to each of the first set of conductive pillars, wherein each of the first set of conductive pillars is electrically connected to each of the first set of circuit elements by the first conductive rail; and a first power cell extending through the substrate, wherein the first power cell includes a first number of power pillars extending through the substrate, wherein each of the first number of power pillars electrically connects to the first conductive rail in parallel.

A fusible structure includes a metal line with different portions having different thicknesses. Thinner portions of the metal line are designed to be destructively altered at lower voltages while thicker portions of the metal line are designed to be destructively altered at lower voltages. Furthermore, one or more dummy structures are disposed proximal to the thinner portions of the metal line. In some embodiments, dummy structures are placed with sufficient proximity so as to protect against metal sputtering when metal line is destructively altered.

A one-time programmable (OTP) memory cell includes a substrate having an active area surrounded by an isolation region. A divot is disposed between the active area and the isolation region. A transistor is disposed on the active area. A diffusion-contact fuse is electrically coupled to the transistor. The diffusion-contact fuse includes a diffusion region in the active area, a silicide layer on the diffusion region, and a contact partially landed on the silicide layer and partially landed on the isolation region. A sidewall surface of the diffusion region in the divot is covered by the silicide layer. The divot is filled with the contact.

An exemplary method includes forming a fuse structure and forming a first cathode connector and a second cathode connector over the fuse structure. The fuse structure includes an anode, a cathode, and a fuse link extending between and connecting the anode and the cathode. The fuse link has a width defined between a first edge and a second edge, which extend a length of the fuse link. The cathode includes a central region defined by a first longitudinal axis and a second longitudinal axis extending respectively from the first edge and the second edge. The first cathode connector and the second cathode connector are equidistant respectively to the fuse link, the first cathode connector does not intersect the first longitudinal axis, and the second cathode connector does not intersect the second longitudinal axis, such that the central region is free of the first cathode connector and the second cathode connector.

Metal fuses and self-aligned gate edge (SAGE) architectures having metal fuses are described. In an example, an integrated circuit structure includes a plurality of semiconductor fins protruding through a trench isolation region above a substrate. A first gate structure is over a first of the plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A gate edge isolation structure is laterally between and in contact with the first gate structure and the second gate structure. The gate edge isolation structure is on the trench isolation region and extends above an uppermost surface of the first gate structure and the second gate structure. A metal fuse is on the gate edge isolation structure.

A semiconductor device and a method of operating the same are provided. The semiconductor device includes a transistor and a fuse structure electrically connected to the transistor. The fuse structure includes a first fuse element, a second fuse element, and a fuse medium. The second fuse element at least partially overlaps the first fuse element. The fuse medium connects the first fuse element and the second fuse element. The fuse medium includes an electrically conductive material.

Disclosed are an integrated circuit device and a formation method thereof. The formation method of an integrated circuit device comprises the following steps: providing a substrate, wherein a first plug and a second plug are disposed inside the substrate; forming a first covering layer covering the substrate; forming, in the first region, a first opening exposing the first plug; forming a first conductive layer in the first opening; forming an isolation layer covering the first conductive layer and the first covering layer; forming, in the first region, a contact hole exposing the first conductive layer and a trench located above the contact hole and connecting with the contact hole, and forming, in the second region, a second opening exposing the second plug; and forming a conductive connection layer in the contact hole, forming a second conductive layer in the trench, and forming a fuse wire in the second opening.

The present disclosure provides a semiconductor structure having a vertical fin with an oxidized sidewall and a method for preparing the semiconductor structure. The semiconductor structure includes a substrate, a top source/drain, a channel fin, a gate structure, a top cathode/anode, and a vertical fin. The substrate has a bottom source/drain and a bottom cathode/anode. The top source/drain is disposed above the bottom source/drain of the substrate, and the channel fin connects the top source/drain to the bottom source/drain of the substrate. The gate structure is disposed on the channel fin. The top cathode/anode is disposed above the bottom cathode/anode of the substrate, and the vertical fin connects the top cathode/anode to the bottom cathode/anode of the substrate, wherein the vertical fin has an oxidized sidewall.

Various semiconductor chips and chip stack arrangements are disclosed. In one aspect, a semiconductor chip stack is provided that includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a first logic layer and a first semiconductor layer on the first logic layer. The first semiconductor layer has plural first through-silicon transistors operable to selectively control the transmission of data from the first semiconductor chip to the second semiconductor chip and has plural first through-silicon vias to convey control signals to the second semiconductor chip.

Systems and methods of manufacture are disclosed for semiconductor device assemblies having a front side metallurgy portion, a substrate layer adjacent to the front side metallurgy portion, a plurality of through-silicon-vias (TSVs) in the substrate layer, metallic conductors located within at least a portion of the plurality of TSVs, and at least one conductive connection circuitry between the metallic conductors and the front side metallurgy portion. The plurality of TSVs with metallic conductors located within are configured to form an antenna structure. Selectively breakable connective circuitry is used to form and/or tune the antenna structure.