Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.

A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

The present disclosure relates to an integrated chip including a semiconductor device. The semiconductor device includes a first source/drain structure, a second source/drain structure, a stack of channel structures, and a gate structure. The stack of channel structures and the gate structure are between the first and second source/drain structures. The gate structure surrounds the stack of channel structures. A first conductive wire overlies and is spaced from the semiconductor device. The first conductive wire includes a first stack of conductive layers. A first conductive contact extends through a dielectric layer from the first conductive wire to the first source/drain structure. The first conductive contact is on a back-side of the first source/drain structure.

An integrated circuit includes a first-voltage power rail and a second-voltage power rail in a first connection layer, and includes a first-voltage underlayer power rail and a second-voltage underlayer power rail below the first connection layer. Each of the first-voltage and second-voltage power rails extends in a second direction that is perpendicular to a first direction. Each of the first-voltage and second-voltage underlayer power rails extends in the first direction. The integrated circuit includes a first via-connector connecting the first-voltage power rail with the first-voltage underlayer power rail, and a second via-connector connecting the second-voltage power rail with the second-voltage underlayer power rail.

A method of fabricating a semiconductor device is disclosed. The method may include forming an etch-target layer, a mask layer, a blocking layer, and a photoresist layer, which are sequentially stacked on a substrate; forming a photoresist pattern, the forming the photoresist pattern including irradiating the photoresist layer with extreme ultraviolet (EUV) light; forming a mask layer, the forming the mask layer including etching the mask layer using the photoresist pattern as an etch mask; and forming a target pattern, the forming the target pattern including etching the etch-target layer using the mask pattern as an etch mask. The photoresist layer may include an organic metal oxide. The blocking layer may be a non-polar layer and may limit and/or prevent a metallic element in the photoresist layer from infiltrating into the mask layer.

Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line in a direction parallel to a backside surface of the first dielectric layer.

Semiconductor device assemblies are provided with a package substrate including one or more layers of thermally conductive material configured to conduct heat generated by one or more of semiconductor dies of the assemblies laterally outward towards an outer edge of the assembly. The layer of thermally conductive material can comprise one or more allotropes of carbon, such as diamond, graphene, graphite, carbon nanotubes, or a combination thereof. The layer of thermally conductive material can be provided via deposition (e.g., sputtering, PVD, CVD, or ALD), via adhering a film comprising the layer of thermally conductive material to an outer surface of the package substrate, or via embedding a film comprising the layer of thermally conductive material to within the package substrate.

Methods and devices including a plurality of memory cells and a first bit line connected to a first column of memory cells of the plurality of memory cells, and a second bit line connected to the first column of cells. The first bit line is shared with a second column of memory cells adjacent to the first column of memory cells. The second bit line is shared with a third column of cells adjacent to the first column of cells opposite the second column of cells.

In some embodiments, an integrated circuit device includes a substrate having a frontside and a backside; one or more active semiconductor devices formed on the frontside of the substrate; conductive paths formed on the frontside of the substrate; and conductive paths formed on the backside of the substrate. At least some of the conductive paths formed on the backside of the substrate, and as least some of the conductive paths formed on the front side of the substrate, are signal paths among the active semiconductor devices. In in some embodiments, other conductive paths formed on the backside of the substrate are power grid lines for powering at least some of the active semiconductor devices.

A semiconductor package includes a substrate, at least one semiconductor chip arranged in the substrate and having chip pads, and a redistribution wiring layer covering a lower surface of the substrate and including first and second redistribution wirings and dummy patterns, the first and second redistribution wirings being stacked in at least two levels and connected to the chip pads. The first and second redistribution wirings are arranged in a redistribution region of the redistribution wiring layer, and the dummy patterns extend in an outer region outside the redistribution region to partially cover corner portions of the redistribution wiring layer, respectively.