A semiconductor device includes a first substrate. The semiconductor device includes a plurality of metallization layers formed over the first substrate. The semiconductor device includes a plurality of via structures formed over the plurality of metallization layers. The semiconductor device includes a second substrate attached to the first substrate through the plurality of via structures. The semiconductor device includes a first conductive line disposed in a first one of the plurality of metallization layers. The first conductive line, extending along a first lateral direction, is connected to at least a first one of the plurality of via structures that is in electrical contact with a first through via structure of the second substrate, and to at least a second one of the plurality of via structures that is laterally offset from the first through via structure.

A semiconductor device includes an active region extending in a first direction; a device isolation layer on side surfaces of the active region and defining the active region; a gate structure intersecting the active region on the active region and extending in a second direction; source/drain regions in regions in which the active region is recessed, on both sides of the gate structure; first protective layers between the device isolation layer and the gate structure; and a buried interconnection line below the source/drain regions and connected to one of the source/drain regions through an upper surface of the buried interconnection line.

A semiconductor integrated circuit device includes a core region and an IO region on a chip. In an IO cell row placed in the IO region, a first power supply line extending in the X direction in a low power supply voltage region has a portion protruding to the core region. A signal IO cell has a reinforcing line that connects a second power supply line extending in the X direction in the low power supply voltage region and a third power supply line extending in the X direction in a high power supply voltage region, the reinforcing line extending in the Y direction in a layer above the second and third power supply lines.

A semiconductor device includes a flip flop cell. The flip flop cell is formed on a semiconductor substrate, includes a flip flop circuit, and comprises a scan mux circuit, a master latch circuit, a slave latch circuit, a clock driver circuit, and an output circuit. Each of the scan mux circuit, the master latch circuit, the slave latch circuit, the clock driver circuit, and the output circuit includes a plurality of active devices which together output a resulting signal for that circuit based on inputs, is a sub-circuit of the flip flop circuit, and occupies a continuously-bounded area of the flip flop circuit from a plan view. At least a first sub-circuit and a second sub-circuit of the sub-circuits overlap from the plan view in a first overlap region, the first overlap region including part of a first continuously-bounded area for the first sub-circuit and part of a second continuously-bounded area for the second sub-circuit.

Semiconductor devices and methods are provided which facilitate performing physical failure analysis (PFA) testing from a backside of the devices. In at least one example, a device is provided that includes a semiconductor device layer including a plurality of diffusion regions. A first interconnection structure is disposed on a first side of the semiconductor device layer, and the first interconnection structure includes at least one electrical contact. A second interconnection structure is disposed on a second side of the semiconductor device layer, and the second interconnection structure includes a plurality of backside power rails. Each of the backside power rails at least partially overlaps a respective diffusion region of the plurality of diffusion regions and defines openings which expose portions of the respective diffusion region at the second side of the semiconductor device layer.

An integrated circuit includes a first cell, a second cell, a buffer zone and a first power rail. The first cell includes a first set of fins extending in a first direction. Each fin of the first set of fins corresponds to a transistor of a first set of transistors. The second cell includes a second set of fins extending in the first direction. Each fin of the second set of fins corresponds to a transistor of a second set of transistors. The second set of fins is separated from the first set of fins in a second direction. The buffer zone is between the first cell and the second cell. The first power rail extends in the first direction, and overlaps at least the buffer zone. The first power rail is in a first metal layer, and is configured to supply a first voltage.

A semiconductor structure includes: a first gate structure and a second gate structure extending in a first direction; a first base level metal interconnect (M0) pattern extending in a second direction perpendicular to the first direction; a second M0 pattern extending in the second direction; a third M0 pattern located between the first and second gate structures and extending in the first direction, two ends of the third M0 pattern connected to the first M0 pattern and the second M0 pattern, respectively; a fourth M0 pattern and a fifth M0 pattern located between the first and second M0 patterns and extending in the second direction. A distance between the fourth M0 pattern and the first M0 pattern in the first direction is equal to a minimum M0 pattern pitch, and a distance between the fourth M0 pattern and the second M0 pattern is equal to the minimum M0 pattern pitch.

A semiconductor device includes a substrate having a first side and a second side. The semiconductor device on the first side includes: an active region that extends along a first lateral direction and comprises a first sub-region and a second sub-region; a first gate structure that extends along a second lateral direction and is disposed over the active region, with the first and second sub-regions disposed on opposite sides of the first gate structure, wherein the second lateral direction is perpendicular to the first lateral direction; and a first interconnecting structure electrically coupled to the first gate structure. The semiconductor device on the second side includes a second interconnecting structure that is electrically coupled to the first and second sub-regions and configured to provide a power supply. The active region, the first gate structure, the first interconnecting structure, and the second interconnecting structure are collectively configured as a decoupling capacitor.

Stacked integrated circuit devices may include standard cells including a first standard cell in a first row and a second standard cell in a second row immediately adjacent to the first row. Each of the standard cells may include an upper transistor and a lower transistor. The upper transistor may include an upper active region, an upper gate structure, and an upper source/drain region. The lower transistor may include a lower active region, a lower gate structure, and a lower source/drain region. Each of the standard cells may also include a power line and a power via electrically connecting the power line to the lower source/drain region. The power via of the first standard cell and the power via of the second standard cell may be aligned with each other along the first direction.

A semiconductor device includes a substrate, a first cell having a first functionality, and a second cell having a second functionality. The first cell includes a first portion on a first side of the substrate, wherein the first portion includes a first conductive element; a second portion on a second side of the substrate, wherein the second portion includes a second conductive element; and a first conductive via extending through the substrate and electrically connecting the first conductive element to the second conductive element. The second cell includes a third portion on the first side of the substrate, wherein the third portion includes a third conductive element; a fourth portion on the second side of the substrate, wherein the fourth portion includes a fourth conductive element; and a second conductive via extending through the substrate and electrically connecting the third conductive element to the fourth conductive element.