A power module having electrical connection parts, preferably made of metal, each having a main plate, the main plates extending in one and the same main plane so as to be substantially coplanar. At least one of the electrical connection parts includes at least one electrical connector projecting from its main plate. At least one transistor is electrically connected between two upper faces of respectively two of the main plates, and an electrically insulating overmolding, for example made of resin, covers each transistor and at least one portion of the upper faces of the main plates.

A manufacturing method of an electronic-component-mounted module includes a step of forming a laminate of: a ceramic substrate board, a circuit layer made of aluminum or aluminum alloy on the ceramic substrate board, a first silver paste layer between the circuit layer and one surface of an electronic component, the electronic component, a lead frame made of copper or copper alloy, and a second silver paste layer between the other surface of the electronic component and the lead frame; and a step of batch-bonding bonding the circuit layer, the electronic component, and the lead frame at one time by heating the laminate to a heating temperature of not less than 180° C. to 350° C. inclusive with adding a pressure of 1 MPa to 20 MPa inclusive in a laminating direction on the laminate, to sinter the first and second silver paste layers and form first and second silver-sintered bonding layers.

In a wiring member, an element connection portion, a plate connection portion, and an upper surface portion are at height positions different from one another. The element connection portion has a through hole, and the plate connection portion has a through hole and a chamfer. The upper surface portion which is not connected to another portion, has projections asymmetrically disposed on both side surfaces thereof. Owing to these features, the type, the orientation, and the front and the back of the wiring member can be easily distinguished. Accordingly, it is possible to prevent incorrect assembling of the wiring member in a semiconductor module.

The present invention provides a packaging method and a packaging structure for a cascode power electronic device, in which a hetero-multiple chip scale package is used to replace the traditional die bonding and wire bonding packaging method. The cascode power electronic device can reduce the inductance resistance and thermal resistance of the connecting wires and reduce the size of the package; and increase the switching frequency of power density. The chip scale package of the present invention uses more than one gallium nitride semiconductor die, more than one diode, and more than one metal oxide semiconductor transistor. The package structure can use TO-220, quad flat package or other shapes and sizes; the encapsulation process of the traditional epoxy molding compounds can be used in low-power applications; and the encapsulation process of ceramic material can be used in high-power applications.

A method of manufacturing a cascode HEMT semiconductor device including a lead frame, a die pad with an indentation attached to the lead frame, and a HEMT die attached to the die pad. The HEMT die includes a HEMT source and a HEMT drain on a first side, and a HEMT gate on a second side. The device further includes a MOSFET die attached to the source of the HEMT die, and the MOSFET die includes a MOSFET source, a MOSFET gate and a MOSFET drain. The MOSFET drain is connected to the HEMT source, and the MOSFET source includes a MOSFET source clip. The MOSFET source clip includes a pillar so to connect the MOSFET source to the HEMT gate, and the connection between the MOSFET source to the HEMT gate is established by a conductive material.

A method of forming a semiconductor device includes providing a power electronics carrier including a structured metallization layer disposed on an electrically insulating substrate, mounting one or more semiconductor dies on a portion of the structured metallization layer, forming an encapsulant body of electrically insulating material that covers the power electronics carrier and encapsulates the one or more semiconductor dies, securing a press-fit connector to the power electronics carrier with a base portion of the press-fit connector being disposed within an opening in the encapsulant body and with an interfacing end of the press-fit connector being electrically accessible from outside the encapsulant body.

A method of forming a semiconductor device includes providing a carrier comprising a die attach pad, providing a semiconductor die that includes a bond pad disposed on a main surface of the semiconductor die, and providing a metal interconnect element, arranging the semiconductor die on the die attach pad such that the bond pad faces away from the die attach pad, and welding the metal interconnect element to the bond pad, wherein the bond pad comprises first and second metal layers, wherein the second metal layer is disposed between the first metal layer and a semiconductor body of the semiconductor die, wherein a thickness of the first metal layer is greater than a thickness of the second metal layer, and wherein the first metal layer has a different metal composition as the second metal layer.

Provided is a semiconductor device including: a circuit board; a wiring pattern; a first semiconductor chip and a second semiconductor chip; a first lead frame; and a second lead frame; wherein the first lead frame and the second lead frame each comprises: a chip joining portion provided above at least a part of the semiconductor chip; a wiring joining portion provided above at least a part of the wiring pattern; and a bridging portion for connecting the chip joining portion and the wiring joining portion; and in the first direction, a space between the bridging portion of the first lead frame and the bridging portion of the second lead frame is smaller than a space between the chip joining portion of the first lead frame and the chip joining portion of the second lead frame.

This semiconductor device includes: a plate-shaped heat dissipation plate; a plurality of switching elements joined to one surface of the heat dissipation plate; a first terminal located apart from the heat dissipation plate, extending in a direction away from the heat dissipation plate, and connected via first conductors to surfaces of the switching elements on a side opposite to the heat dissipation plate side; and a sealing member sealing the switching elements, the heat dissipation plate, and the first terminal. A cutout is provided at an outer periphery of the heat dissipation plate. A part of the first terminal on the heat dissipation plate side overlaps a cut-out area at the cutout as seen in a direction perpendicular to the one surface of the heat dissipation plate. A retracted portion retracted inward is formed at an outer periphery of another surface of the heat dissipation plate.

This semiconductor device includes: a heat dissipation plate formed in a plate shape; a plurality of switching elements joined to one surface of the heat dissipation plate; a first terminal extending in a direction away from the heat dissipation plate in a state of being apart from the heat dissipation plate, the first terminal being connected via a first electric conductor to surfaces of the plurality of switching elements on an opposite side to the heat dissipation plate side; and a sealing member sealing the plurality of switching elements, the heat dissipation plate, and the first terminal. A notch is provided in an outer periphery portion of the heat dissipation plate. A portion of the first terminal on the heat dissipation plate side overlaps with a region of a cut at the notch as seen in a direction perpendicular to the one surface of the heat dissipation plate.