According to one or more embodiments, an intelligent solar racking system is provided. The intelligent solar racking system includes a racking frame that receives and mechanically supports solar modules. The intelligent solar racking system includes sensors distributed throughout the racking frame. Each of the sensors detects and reports parameter data by generating output signals. The sensors include module sensors positioned to associate with each of the solar modules and detect a module presence as the parameter data for the solar modules. The intelligent solar racking system includes a computing device that receives, stores, and analyzes the output signals to determine and monitor operations of the intelligent solar racking system.

Provided are a solid-state imaging device, a manufacturing method thereof, and an electronic device. The solid-state imaging device includes a first semiconductor layer in which a first photoelectric conversion unit and a first floating diffusion are formed, a second semiconductor layer in which a second photoelectric conversion unit and a second floating diffusion are formed, and a wiring layer including a wiring electrically connected to the first and second floating diffusions. The first semiconductor layer and the second semiconductor layer are laminated, and the wiring layer is formed on a side of the first or second semiconductor layer, the side being opposite to a side on which the first semiconductor layer and the second semiconductor layer face each other.

Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

A device is provided. The device includes mechanically stacked layers. The mechanically stacked layers include a bottom layer and upper layers. Each upper layer includes a transmissive solar cell that converts light energy into electricity. Each upper layer transmits unconverted portions of the light energy towards the bottom layer. The bottom layer includes a solar cell that converts the unconverted portions of the light energy into electricity.

A solar module racking system including a frame. The frame includes pre-wired receptacles for rapid assembly of solar modules. The frame receives and mechanically supports each solar module. The frame arranges the solar modules in a first planar direction, in a second planar direction, and in a vertical direction that is normal to the first and second planar directions. Each pre-wired receptacles individually and electrically connect each of the solar modules after insertion of that module into the frame. The solar module racking system provides a 2 by 1 by 1 configuration or a 1 by 2 by 1 configuration for the plurality of solar modules corresponding to the first planar direction, the second planar direction, and the vertical direction. A first module and a second module are arranged in the first planar direction or the second planar direction, respectively.

The present disclosure provides a semiconductor package structure. The semiconductor package structure includes a first die, at least a second die, an RDL disposed over the second die, a molding encapsulating the first die and the second die, a plurality of first conductors disposed in the molding, and a plurality of second conductors disposed in the second die. The first die has a first side and a second side opposite to the first side. The second die has a third side facing the first side of the first die and a fourth side opposite to the third side. The RDL is disposed on the fourth side of the second die. The first die is electrically connected to the RDL through the plurality of first conductors, and the second die is electrically connected to the RDL through the plurality of second conductors.

Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

A semiconductor apparatus includes a channel layer, a barrier layer, a source contact and a drain contact, a first doped group III-V semiconductor, a group III-V semiconductor, and a second doped group III-V semiconductor. The barrier layer is disposed on the channel layer. The source contact and the drain contact are disposed on the channel layer. The first doped group III-V semiconductor is disposed on the barrier layer. The group III-V semiconductor is disposed on the first doped group III-V semiconductor and between the source contact and the drain contact. The second doped group III-V semiconductor is disposed on the group III-V semiconductor and between the source contact and the drain contact. The group III-V semiconductor has a central region covered by the second doped group III-V semiconductor and a peripheral region free from coverage by the second doped group III-V semiconductor.

Some embodiments provide a three-dimensional (3D) circuit structure that has two or more vertically stacked bonded layers with a machine-trained network on at least one bonded layer. As described above, each bonded layer can be an IC die or an IC wafer in some embodiments with different embodiments encompassing different combinations of wafers and dies for the different bonded layers. The machine-trained network in some embodiments includes several stages of machine-trained processing nodes with routing fabric that supplies the outputs of earlier stage nodes to drive the inputs of later stage nodes. In some embodiments, the machine-trained network is a neural network and the processing nodes are neurons of the neural network. In some embodiments, one or more parameters associated with each processing node (e.g., each neuron) is defined through machine-trained processes that define the values of these parameters in order to allow the machine-trained network (e.g., neural network) to perform particular operations (e.g., face recognition, voice recognition, etc.). For example, in some embodiments, the machine-trained parameters are weight values that are used to aggregate (e.g., to sum) several output values of several earlier stage processing nodes to produce an input value for a later stage processing node.

A light emitting diode (LED) pixel for a display including a light emitting structure configured to generate light and comprising at least one active layer, a first passivation layer surrounding side surfaces and an upper portion of the light emitting structure, the first passivation layer including via holes, and a plurality of via contacts filling the via holes and electrically connected to the light emitting structure, in which the via holes do not overlap the at least one active layer, and an area of the first passivation layer is greater than that of the light emitting structure in plan view.