A light emitting diode pixel for a display including a substrate, a first LED sub-unit disposed on the substrate, a second LED sub-unit disposed on the first LED sub-unit, a third LED sub-unit disposed on at least one of the first and second LED sub-units, and vias formed in the substrate, in which each of the first to third LED sub-units comprises a first conductivity type semiconductor layer and a second conductivity type semiconductor layer, and each of the vias is electrically connected to at least one of the first, second, and third LED sub-units.

There is provided an imaging device capable of further improving image quality of a subject, particularly a lesion portion such as cancer. There is provided an imaging device including: a first substrate including a first pixel array unit in which a plurality of pixels having at least a first photoelectric conversion unit is arranged in a two-dimensional manner, a first wiring layer, and a first support layer stacked in this order; and a second substrate including a second pixel array unit in which a plurality of pixels having at least a second photoelectric conversion unit is arranged in a two-dimensional manner, a second wiring layer, and a second support layer stacked in this order, in which the first support layer and the second support layer are bonded to each other to form a stacked structure, and at least one of the support layers includes an antireflection layer.

Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by vertically stacking two or more integrated circuit (IC) dies to at least partially overlap. In this arrangement, several circuit blocks defined on each die (1) overlap with other circuit blocks defined on one or more other dies, and (2) electrically connect to these other circuit blocks through connections that cross one or more bonding layers that bond one or more pairs of dies. In some embodiments, the overlapping, connected circuit block pairs include pairs of computation blocks and pairs of computation and memory blocks. The connections that cross bonding layers to electrically connect circuit blocks on different dies are referred to below as z-axis wiring or connections. This is because these connections traverse completely or mostly in the z-axis of the 3D circuit, with the x-y axes of the 3D circuit defining the planar surface of the IC die substrate or interconnect layers. These connections are also referred to as vertical connections to differentiate them from the horizontal planar connections along the interconnect layers of the IC dies.

A stacked photoplethysmography (PPG) sensor for oximetry is capable of sensing simultaneously, with optimal area and quantum efficiency, PPG signals using a plurality of emission wavelengths without the need for time division multiplexing.

The present technology relates to a solid-state imaging device, a manufacturing method thereof, and an electronic device that enable improvement of the sensitivity in a near infrared region by a simpler process. A solid-state imaging device includes: a first semiconductor layer in which a first photoelectric conversion unit and a first floating diffusion are formed; a second semiconductor layer in which a second photoelectric conversion unit and a second floating diffusion are formed; and a wiring layer including a wiring electrically connected to the first and second floating diffusions. The first semiconductor layer and the second semiconductor layer are laminated, and the wiring layer is formed on a side of the first or second semiconductor layer, the side being opposite to a side on which the first semiconductor layer and the second semiconductor layer face each other. The present technology can be applied to a CMOS image sensor.

In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first image sensor disposed within a first substrate and a second image sensor disposed within a second substrate. The second substrate has a first side facing the first substrate. The first side includes angled surfaces defining one or more recesses within the first side. A band-pass filter is arranged between the first substrate and the second substrate and is configured to reflect electromagnetic radiation that is within a first range of wavelengths.

A semiconductor apparatus and a fabrication method thereof are disclosed. The semiconductor apparatus includes a substrate, a channel layer, a barrier layer, and a gate structure, and includes: a first doped group III-V semiconductor, a group III-V semiconductor, and a conductor. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The first doped group III-V semiconductor is disposed on the barrier layer. The group III-V semiconductor is disposed on the doped group III-V semiconductor. The conductor is disposed on the group III-V semiconductor, where a width of the first doped group III-V semiconductor is greater than a width of the conductor.

Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by vertically stacking two or more integrated circuit (IC) dies to at least partially overlap. In this arrangement, several circuit blocks defined on each die (1) overlap with other circuit blocks defined on one or more other dies, and (2) electrically connect to these other circuit blocks through connections that cross one or more bonding layers that bond one or more pairs of dies. In some embodiments, the overlapping, connected circuit block pairs include pairs of computation blocks and pairs of computation and memory blocks. The connections that cross bonding layers to electrically connect circuit blocks on different dies are referred to below as z-axis wiring or connections. This is because these connections traverse completely or mostly in the z-axis of the 3D circuit, with the x-y axes of the 3D circuit defining the planar surface of the IC die substrate or interconnect layers. These connections are also referred to as vertical connections to differentiate them from the horizontal planar connections along the interconnect layers of the IC dies.

A method includes forming a stacked structure of a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked in a first direction over a substrate, the first semiconductor layers being thicker than the second semiconductor layers. The method also includes patterning the stacked structure into a first fin structure and a second fin structure extending along a second direction substantially perpendicular to the first direction. The method further includes removing the first semiconductor layers of the first fin structure to form a plurality of nanowires. Each of the nanowires has a first height, there is a distance between two adjacent nanowires along the vertical direction, and the distance is greater than the first height. The method includes forming a first gate structure between the second semiconductor layers of the first fin structure.

To improve the joining strength between semiconductor chips. In a semiconductor device, a first semiconductor chip includes a first joining surface including a first insulating layer, a plurality of first pads to which a first inner layer circuit insulated by the first insulating layer is electrically connected, and a linear first metal layer arranged on an outside of the plurality of first pads. A second semiconductor chip includes a second joining surface joined to the first joining surface, the second joining surface including a second insulating layer, a plurality of second pads that are arranged in positions facing the first pads and to which a second inner layer circuit insulated by the second insulating layer is electrically connected, and a linear second metal layer arranged in a position facing the first metal layer. A width of the first metal layer and the second metal layer is a width based on a joining strength between the first insulating layer and the second insulating layer and a joining strength between the first metal layer and the second metal layer in an area from an end portion of the first semiconductor chip to the first pad.