A semiconductor device is provided. A semiconductor device includes a first and a second region, a dielectric layer, a capping layer, and a planar resistive layer. The dielectric layer is arranged over the first and second regions and the capping layer is arranged over the dielectric layer. The capping layer has a substantially planar top surface over the first and second regions. The planar resistive layer is encapsulated within the capping layer in the first device region.

An edge incident type light receiving element unit capable of receiving optical signals in different wavelength ranges incident from the edge side comprises a first light receiving element for receiving optical signals in a first wavelength range and a second light receiving element for receiving optical signals in a second wavelength range, and configured so that optical signals transmitted through a first light receiving portion formed vertically on a wall portion of a first semiconductor substrate incident via a reflecting portion on a second light receiving portion formed on a second semiconductor substrate fitted on the first semiconductor substrate.

The light receiving element unit includes a first light receiving element having a light receiving region on the main surface side of the first semiconductor substrate and a second light receiving element having a light receiving region on the main surface side of the second semiconductor substrate, and a support substrate having wiring for electrically connecting the first light receiving element and the second light receiving element to the outside, one of the first light receiving element and the second light receiving element has a recess formed in a concave shape from the back surface opposite to the light receiving region toward the light receiving region, and the other is accommodated in the recess.

A semiconductor package structure includes a first package, a second package over the first package, a plurality of connectors between the first package and the second package and a plurality of baffle structures between the first package and the second package. The second package includes a bonding region and a periphery region surrounding the bonding region. The connectors are disposed in the bonding region to provide electrical connections between the first package and the second package. The baffle structures are disposed in the periphery region and are separated from each other.

A stacked-die image sensor may be provided with an array of image pixels. The stacked-die image sensor may include at least first and second integrated circuit dies stacked on top of one another. Some of the pixel circuitry in each pixel may be formed in the first integrated circuit die and some of the pixel circuitry in each pixel may be formed in the second integrated circuit die. Coupling structures such as conductive pads may electrically couple the pixel circuitry in the first integrated circuit die to the pixel circuitry in the second integrated circuit die. A shielding structure may partially or completely surround each conductive pad to reduce parasitic capacitive coupling between adjacent conductive pads. The shielding structure may be a metal wire coupled to a ground voltage. The shielding structure may extend between columns of image pixels and/or between rows of image pixels.

To improve the joining strength between semiconductor chips. In a semiconductor device, a first semiconductor chip includes a first joining surface including a first insulating layer, a plurality of first pads to which a first inner layer circuit insulated by the first insulating layer is electrically connected, and a linear first metal layer arranged on an outside of the plurality of first pads. A second semiconductor chip includes a second joining surface joined to the first joining surface, the second joining surface including a second insulating layer, a plurality of second pads that are arranged in positions facing the first pads and to which a second inner layer circuit insulated by the second insulating layer is electrically connected, and a linear second metal layer arranged in a position facing the first metal layer. A width of the first metal layer and the second metal layer is a width based on a joining strength between the first insulating layer and the second insulating layer and a joining strength between the first metal layer and the second metal layer in an area from an end portion of the first semiconductor chip to the first pad.

The light receiving element unit includes a first light receiving element having a light receiving region on the main surface side of the first semiconductor substrate and a second light receiving element having a light receiving region on the main surface side of the second semiconductor substrate, and a support substrate having wiring for electrically connecting the first light receiving element and the second light receiving element to the outside, one of the first light receiving element and the second light receiving element has a recess formed in a concave shape from the back surface opposite to the light receiving region toward the light receiving region, and the other is accommodated in the recess.

An electronic device includes a first module and a second module stacked upon the first module in a stacking direction. The first module includes a pixel substrate and a counter substrate disposed opposite to each other. The pixel substrate is defined with a plurality of pixels. The second module is disposed at one side of the first module adjacent to the counter substrate and away from the pixel substrate. The second module includes a plurality of micro-photoelectric units and a protection layer. The protection layer stacks upon the micro-photoelectric units and is disposed at one side of the second module away from the first module. Each of the micro-photoelectric units unshields one or more of the pixels in the stacking direction. Each micro-photoelectric unit includes a micro-photoelectric element, and at least one of the micro-photoelectric elements is a sensor element.

A device of acquisition of a 2D image and of a depth image, including: first sensor formed inside and on top of a first semiconductor substrate including a front surface and a rear surface, the first sensor including a plurality of 2D image pixels and a plurality of transmissive windows, each transmissive window including a portion of the first substrate and an amorphous silicon region in contact with the rear surface of said portion of the first substrate; and against the first sensor on the rear surface side of the first substrate, a second sensor formed inside and on top of a second semiconductor substrate and including a plurality of depth pixels arranged opposite the transmissive windows of the first sensor.

An electrostatic discharge (ESD) protection circuit includes a first diode, a second diode and an ESD clamp circuit. The first diode is in a semiconductor wafer, and is coupled to an input output (IO) pad. The second diode is in the semiconductor wafer, and is coupled to the first diode and the IO pad. The ESD clamp circuit is in the semiconductor wafer, and is coupled to the first diode and the second diode. The ESD clamp circuit includes a first signal tap region in the semiconductor wafer. The first signal tap region is coupled to a first voltage supply. The first diode is coupled to and configured to share the first signal tap region with the ESD clamp circuit.