The technology of this application relates to a semiconductor packaged structure, including a circuit board, a chip, a pin, and a plastic package body. The pin includes a connecting part and a pressfit, one end of the connecting part is welded to the circuit board, the other end is flush with a top surface of the plastic package body, the connecting part has a mounting hole, the pressfit is disposed in the mounting hole and is in an interference fit with the connecting part, the pressfit is exposed from the top surface of the plastic package body. Alternatively, the pin includes a pressfit, the plastic package body is provided with a mounting hole that runs through a plastic package body, the pressfit is provided in the mounting hole, one end of the pressfit is welded to the circuit board, the other end is exposed from the top surface of the plastic package body.

A printed circuit board including a dielectric insulation layer having a top side facing a first side and a bottom side opposite the first side that faces a second side of the dielectric insulation layer, at least one conducting track formed on the dielectric insulation layer, and one or more conductor rails, wherein each of the one or more conductor rails is mechanically coupled to the dielectric insulation layer, and a first portion of each of the one or more conductor rails is arranged on the first side and a second portion of each of the one or more conductor rails is arranged on the second side of the dielectric insulation layer.

A semiconductor device includes a cooling base board and an insulated circuit substrate. On a front surface of an insulated board on the insulated circuit substrate, a high potential circuit pattern on which a semiconductor chip is mounted, an intermediate potential circuit pattern on which a semiconductor chip is mounted, a low potential circuit pattern, and a control circuit pattern are disposed so as to straddle a center line of the cooling base board. The intermediate potential circuit pattern includes a second chip mounting region, an output wiring connection region and an interconnect wiring region that form a U-shaped portion in which the high potential circuit pattern having a semiconductor chip thereon is disposed. The control circuit pattern is disposed so as to straddle the center line and faces the opening of the U-shaped portion.

A semiconductor device includes a semiconductor chip, a bonding member, and a planar laminated substrate having the semiconductor chip bonded to a front surface thereof via the bonding member. The laminated substrate includes a planar ceramic board, a high-potential metal layer, a low-potential metal layer, an intermediate layer. The planar ceramic board contains a plurality of ceramic particles. The high-potential metal layer contains copper and is bonded to a first main surface of the ceramic board. The low-potential metal layer contains copper, is bonded to a second main surface of the ceramic board, and has a potential lower than a potential of the first main surface of the high-potential metal layer. The intermediate layer is provided between the second main surface and the low-potential metal layer and includes a first oxide that contains at least either magnesium or manganese.

A semiconductor device package comprises a semiconductor switching device having a body, including a first side, and an opposing second side coupled to a substrate. A gate terminal is defined on the semiconductor switching device body first side, the gate terminal having a first side, and an opposing second side facing the semiconductor switching device body. A first gate resistor is disposed on the gate terminal first side, and coupled electrically in series with the gate terminal.

Implementations of semiconductor packages may include: a die coupled to a substrate; a housing coupled to the substrate and at least partially enclosing the die within a cavity of the housing, and; a pin fixedly coupled to the housing and electrically coupled with the die, wherein the pin includes a reversibly elastically deformable lower portion configured to compress to prevent a lower end of the pin from lowering beyond a predetermined point relative to the substrate when the housing is lowered to be coupled to the substrate.

A semiconductor device includes: a housing; a substrate inside the housing; first and second semiconductor circuits on the substrate; and first and second planar terminals electrically connected to the first and second semiconductor circuits, respectively, the first and second planar terminals stacked on top of each other, wherein each of the first and second planar terminals extends away from the housing.

A semiconductor device includes a first electrode; a second electrode; a resin case surrounding the first electrode and the second electrode; and a resin insulating part made of a material the same as a material of the resin case and covering part of the first electrode and part of the second electrode inside the resin case. The resin insulating part contacts an inner wall of the resin case or is separated from the inner wall of the resin case. A move positioned between the first electrode and the second electrode is formed at the resin insulating part, and thus a space in which the resin insulating part does not exist or a material different from the resin insulating part is provided between the first electrode and the second electrode.

A rectangular power module with a body having two short ends defining a length and two long sides defining a width having three parallel circuit paths crossing the short width distance from side to side using side positioned gate terminals and planar top positioned top power terminal positioned between MOSFETS in the circuit for even thermal positioning and reduced current path, inductance, and resistance and increased power density.

The resin material 336 is arranged in a first region 421 surrounded by the fin base 440, the inclined portion 343 of the cover member 340, and the outermost peripheral heat dissipation fins 334 arranged on the outermost peripheral side. Then, the resin material 336 is caused to protrude to the first region 421. That is, the resin material 336 is arranged in the first region 421. In a cross section perpendicular to the refrigerant flow direction (Y direction), a cross-sectional area of the first region 421 is larger than an average cross-sectional area 423 of the adjacent heat dissipation fins 331. Then, a cross-sectional area of a second region 422 formed between the resin material 336 arranged in the first region 421 and the outermost peripheral heat dissipation fin 334 arranged on the outermost peripheral side is smaller than the average cross-sectional area 423 of the heat dissipation fins.