A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.

Various embodiments of the teachings herein include power electronic circuits comprising: interconnected power modules, each with a power electronic element and a plurality of capacitors in parallel. The power electronic elements are mounted on a first side of substrate plates. The capacitors are mounted in a plurality of planes one above the other on a second side of the substrate plates. The substrate plates, with the power electronic elements forward and alongside each other, are fixed onto an assembly side of a base circuit carrier.

A power converter includes a power card that houses switching elements therein, an electrically conductive cooler that is in contact with the power card with an insulation plate disposed between the cooler and the power card, and a grounded electrically conductive case that houses the power card and the cooler therein, wherein the power converter converts power through switching operation of the switching elements, and wherein the cooler is attached to the case with an insulation spacer and an insulation tube disposed between the cooler and the case.

A high current solid-state bidirectional relay assembly includes a first conductor bar, a second conductor bar, and a third intermediate conductor bar. A plurality of MOSFET switching elements are disposed in two back-to-back arrays of switching elements. Either all of the source leads or all of the drain leads of the plurality of MOSFET switching element are electrically connected to the third intermediate conductor bar. The other leads of each MOSFET switching element in one of the arrays are electrically connected to the first conductor bar, and the other leads of each MOSFET switching element in the other array are electrically connected to the second conductor bar. A printed circuit board has control circuitry to control the bidirectional relay. All of the gate leads of the plurality of MOSFET switching elements are electrically connected to the control circuitry of the printed circuit board.

Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.

Various embodiments of the teachings herein include power electronic circuits comprising: interconnected power modules, each with a power electronic element and a plurality of capacitors in parallel. The power electronic elements are mounted on a first side of substrate plates. The capacitors are mounted in a plurality of planes one above the other on a second side of the substrate plates. The substrate plates, with the power electronic elements forward and alongside each other, are fixed onto an assembly side of a base circuit carrier.

A semiconductor device includes first and second chips that are stacked such that first surfaces of their element layers face each other. Each chip has a substrate, an element layer on a first surface of the substrate, pads on the element layer, and vias that penetrate through the substrate and the element layer. Each via is exposed from a second surface of the substrate and directly connected to one of the pads. The vias include a first via of the first chip directly connected to a first pad of the first chip and a second via of the second chip directly connected to a second pad of the second chip. The pads further include a third pad of the second chip which is electrically connected to the second pad by a wiring in the element layer of the second chip and to the first pad through a micro-bump.

A semiconductor device includes an interposer disposed on a substrate. A first major surface of the interposer faces the substrate. A system on a chip is disposed on a second major surface of the interposer. The second major surface of the interposer opposes the first major surface of the interposer. A plurality of first passive devices is disposed in the first major surface of the interposer. A plurality of second passive devices is disposed on the second major surface of the interposer. The second passive devices are different devices than the first passive devices.

The invention relates to a three-dimensional electronic module comprising an electronic device housed between a first substrate and a second substrate, said first and second substrates being electrically and/or thermally connected to one another by at least one and preferably two heat bridges added onto and rigidly connected to said first and second substrates. The invention also relates to an electronic system comprising at least two electronic modules mounted facing one another so as to sandwich a third substrate in contact with the second substrate thereof, respectively. The third substrate is configured to provide thermal and electrical coupling between the two electronic modules via the second substrate (140) thereof.

A power module is applied to an electric power conversion device in which multiple upper-lower arm circuits are connected to an electric power line in parallel. The power module includes the multiple upper-lower arm circuits; a capacitor connected to each of the multiple upper-lower arm circuits in parallel; an upper wiring that connects an upper arm and a positive electrode terminal of the capacitor; a lower wiring that connects a lower arm and a negative electrode of the capacitor; an upper electric power wiring that is an electric power wiring connected to the electric power line and connects a high potential line of the electric power line and the upper wiring; and a lower electric power wiring that is an electric power wiring connected to the electric power line and connects a lower potential line of the electric power line and the lower wiring.