The present disclosure provides a wafer level packaging method and a package structure. The wafer level packaging method includes: forming a bonding structure including a device wafer and a plurality of first chips bonded to the device wafer; conformally covering the plurality of first chips and the device wafer exposed by the plurality of first chips with an insulating layer; conformally covering the insulating layer with a shielding layer; and forming an encapsulation layer on the shielding layer. The wafer level package structure includes: a device wafer; a plurality of first chips bonded to the device wafer; an insulating layer conformally covering the plurality of first chips and the device wafer exposed by the plurality of first chips; a shielding layer conformally covering the insulating layer; and an encapsulation layer formed on the shielding layer. The wafer level package structure provides a reduced volume and a reduced thickness.

A semiconductor module includes a first power semiconductor element having a first surface and a second surface. The semiconductor module also includes a second power semiconductor element having a first surface and a second surface. The semiconductor module also includes first, second, third, and fourth conductor plates, and a connecting part. The connecting part is integrally formed with the second conductor plate, extends toward the third conductor plate, and is connected to the third conductor plate.

The present invention relates to a spring element for a power semiconductor module, wherein the spring element includes a first part made from a first material and a second part made from a second material, the first material being different from the second material, wherein the first part comprises both a first contact portion having a first contact and a second contact portion having a second contact, wherein the first part comprises an electrically conductive path formed from the first contact portion to the second contact portion, and wherein the second part is adapted for exerting a spring force (FS) onto the first contact portion and the second contact portion for pressing the first contact to a first contact area of a power semiconductor module and the second contact to a second contact area of a power semiconductor module. Such a spring element may form a press contact in a power semiconductor module and may be less bulky compared to solutions in the prior art and may be formed cost-sparingly.

A semiconductor device includes first and second chips that are stacked such that first surfaces of their element layers face each other. Each chip has a substrate, an element layer on a first surface of the substrate, pads on the element layer, and vias that penetrate through the substrate and the element layer. Each via is exposed from a second surface of the substrate and directly connected to one of the pads. The vias include a first via of the first chip directly connected to a first pad of the first chip and a second via of the second chip directly connected to a second pad of the second chip. The pads further include a third pad of the second chip which is electrically connected to the second pad by a wiring in the element layer of the second chip and to the first pad through a micro-bump.

A semiconductor package includes a silicon substrate including a cavity and a plurality of through holes spaced apart from the cavity, a first semiconductor chip in the cavity, a plurality of conductive vias in the plurality of through holes, a first redistribution layer on the silicon substrate and connected to the first semiconductor chip and the conductive vias, and a second redistribution layer below the silicon substrate and connected to the first semiconductor chip and the plurality of conductive vias.

Described is a semiconductor substrate stack, comprising: a plurality of semiconductor substrates arranged in a stack in which the semiconductor substrates include opposing facing surfaces, wherein the facing surfaces of adjacent semiconductor substrates are separated by a gap, each semiconductor substrate having an edge surface at an exposed edge of the stack. A spacer is attached to one of the facing surfaces of each of the at least one of the semiconductor substrates and extends between adjacent semiconductor substrates to define the gap and mask a central portion of each respective semiconductor substrate.

A power semiconductor device includes a first power semiconductor element, a second power semiconductor element, a first conductor plate, a second conductor plate, a third conductor plate, and a fourth conductor plate. The power semiconductor device also includes a DC positive terminal, a DC negative terminal, an AC terminal, and a sealing member that integrally seals the first conductor plate, the second conductor plate, the third conductor plate, and the fourth conductor plate. Each of the DC positive terminal, the DC negative terminal, and the AC terminal has a cut section formed by cutting a tie bar that integrally couples the DC positive terminal, the DC negative terminal, and the AC terminal.

A power module is applied to an electric power conversion device in which multiple upper-lower arm circuits are connected to an electric power line in parallel. The power module includes the multiple upper-lower arm circuits; a capacitor connected to each of the multiple upper-lower arm circuits in parallel; an upper wiring that connects an upper arm and a positive electrode terminal of the capacitor; a lower wiring that connects a lower arm and a negative electrode of the capacitor; an upper electric power wiring that is an electric power wiring connected to the electric power line and connects a high potential line of the electric power line and the upper wiring; and a lower electric power wiring that is an electric power wiring connected to the electric power line and connects a lower potential line of the electric power line and the lower wiring.

A voltage regulating module design is provided. In one aspect, a voltage regulating module (VRM) includes a first layer configured to output a regulated voltage that is based on a stepped down voltage, and a second layer stacked with the first layer, and a plurality of contacts, such as a ball grid array (BGA), on the first layer. The second layer includes a plurality of active components configured to provide the stepped down voltage to the first layer. The first and second layers have overlapping recesses, and the recess of the first layer has a larger footprint than the recess of the second layer. A plurality of the VRMS can be arranged to form an opening including a counterbore. A faster, such as a bolt, can be positioned in the opening. The first layer can have a larger clearance from the fastener positioned in the opening than the second layer.

A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.