A semiconductor device, including a plurality of semiconductor units disposed in a matrix, and a capsule encapsulating the plurality of semiconductor units. Each semiconductor unit includes a semiconductor element and another capsule encapsulating the semiconductor element. Each semiconductor unit further has a plurality of convex portions formed on a front surface thereof, and an engagement portion through which the semiconductor unit engages with at least one of the other semiconductor units.

There are disclosed herein various implementations of a compact high-voltage semiconductor package. In one exemplary implementation, such a semiconductor package includes a power transistor, as well as a drain contact, a source contact, and a gate contact to provide external connections to the power transistor. The semiconductor package also includes a contour element formed between the drain contact and the source contact in the semiconductor package. The contour element increases a creepage distance between the drain contact and the source contact in the semiconductor package so as to increase a breakdown voltage of the semiconductor package.

A power semiconductor module includes a wiring member that electrically connects a front surface electrode of a semiconductor element and a circuit board of an insulating substrate in a housing. A resin provided in the housing covers the wiring member, and has a height in the vicinity of the wiring member. A cover covering the periphery of external terminals is provided between the resin and a first lid in the housing. A second lid is provided further outside the first lid in an aperture portion of the housing, and the space between the second lid and the first lid is filled with another resin.

A semiconductor apparatus includes: a first conductor plate; a second conductor plate separated from the first conductor plate; a plurality of semiconductor devices having back surface electrodes connected to the first conductor plate; a relay substrate mounted on the second conductor plate and including a plurality of first relay pads and a second relay pad connected to the plurality of first relay pads; a plurality of metal wires respectively connecting control electrodes of the plurality of semiconductor devices to the plurality of first relay pads; a first conductor block connected to front surface electrodes of the plurality of semiconductor devices; a second conductor block connected to the second relay pad; and a sealing material sealing the first and second conductor plates, the plurality of semiconductor devices, the relay substrate, the metal wire, and the first and second conductor blocks, the sealing material includes a first principal surface and a second principal surface opposed to each other, the first conductor plate is exposed from the first principal surface, the second conductor plate is not exposed from the first principal surface, and the first and second conductor blocks are exposed from the second principal surface.

A manufacturing method for a power module capable of shortening a manufacturing time for a power module is obtained. The manufacturing method for a power module includes: a subassembly arranging step of placing a subassembly including a first electrode, a semiconductor device, and a second electrode on a heat sink via a joining material; and a transfer molding step of, after the subassembly arranging step, under a state in which the first electrode, the semiconductor device, and a second-electrode inner portion are arranged in a region surrounded by the heat sink and a molding die, injecting a thermoplastic resin into the region, wherein, in the transfer molding step, the subassembly is joined to the heat sink via the joining material with use of the resin.

A pre-packaged chip includes a chip having at least one electrical top contact at a top side of the chip and at least one electrical bottom contact at a bottom side, a first laminate layer on the top side, a second laminate layer on the bottom side, the first laminate layer and the second laminate layer being laminated together to sandwich the chip therebetween, a first metal layer on the first laminate layer and electrically contacted to the at least one electrical top contact via at least one top contact hole through the first laminate layer, and a second metal layer on the second laminate layer and electrically contacted to the at least one electrical bottom contact via at least one bottom contact hole through the second laminate layer. The pre-packaged chip is free from any contact hole extending from the first metal layer to the second metal layer.

The present invention is directed to provide a semiconductor module capable of achieving miniaturization and reduced manufacturing cost while suppressing surge voltage generated when switching the semiconductor elements. A semiconductor module includes a negative terminal and a positive terminal. The negative terminal has a negative fastening portion for fastening a negative polarity-side external terminal, a negative connection portion connected to a laminated substrate, and a negative intermediate portion arranged between the negative fastening portion and the negative connection portion. The positive terminal has a positive fastening portion for fastening a positive polarity-side external terminal, positive connection portions connected to the laminated substrate, and a positive intermediate portion facing the negative intermediate portion with a predetermined gap and arranged between the positive fastening portion and the positive connection portions.

Composite materials including a thin-film layer of lateral p-n junctions can be employed in circuits or various components of electrical devices. A composite material comprises a thin-film layer including p-type regions alternating with n-type regions along a face of the thin-film layer, the p-type regions comprising electrically conductive particles dispersed in a first organic carrier and the n-type regions comprising electrically conductive particles dispersed in a second organic carrier, wherein p-n junctions are established at interfaces between the p-type and n-type regions.

Low inductance power modules for ultra-fast wide-bandgap semiconductor power switching devices are disclosed. Conductive tracks define power buses for a switching topology, e.g. comprising GaN E-HEMTs, with power terminals extending from the power buses through the housing to provide a heatsink-to-busbar distance which meets creepage and clearance requirements. Low-profile, low-inductance terminals for gate and source-sense connections extend from contact areas located adjacent each power switching device to provide for a low inductance gate drive loop, for high di/dt switching. The gate driver board is mounted on the low-profile terminals, inside or outside of the housing, with decoupling capacitors provided on the driver board. For paralleled switches, additional terminals, which are referred to as dynamic performance pins, are provided to the power buses. These pins are configured to provide a low inductance path for high-frequency current and balance inductances of the power commutation loops for each switch.

A power module includes a number of sub-modules connected via removable jumpers. The removable jumpers allow the connections between one or more power semiconductor die in the sub-modules to be reconfigured, such that when the removable jumpers are provided, the power module has a first function, and when the removable jumpers are removed, the power module has a second function. The removable jumpers may also allow for independent testing of the sub-modules. The power module may also include a multi-layer printed circuit board (PCB), which is used to connect one or more contacts of the power semiconductor die. The multi-layer PCB reduces stray inductance between the contacts and therefore improves the performance of the power module.