A packaging technology in which power switching elements, such as field-effect transistors (FETs), can be oriented in a vertical position relative to the printed circuit board (PCB) on which the product is mounted. The power die including the switching element(s) can essentially stand “on end” so that they take up very little PCB area. Multiple dies can be positioned this way, and the dies can be attached to a heat sink structure, which is designed to take the heat generated by the dies onto the top of the package. The heat sink structure can be attached to a structure to route the power and analog signals properly to the desired pins/leads/balls of the finished product. Using these techniques can result in a significant increase in the power density (both PCB space and solution volume) of power switching elements, e.g., FETs.

A package includes a redistribution structure, a die package on a first side of the redistribution structure including a first die connected to a second die by metal-to-metal bonding and dielectric-to-dielectric bonding, a dielectric material over the first die and the second die and surrounding the first die, and a first through via extending through the dielectric material and connected to the first die and a first via of the redistribution structure, a semiconductor device on the first side of the redistribution structure includes a conductive connector, wherein a second via of the redistribution structure contacts the conductive connector of the semiconductor device, a first molding material on the redistribution structure and surrounding the die package and the semiconductor device, and a package through via extending through the first molding material to contact a third via of the redistribution structure.

A semiconductor package includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first alignment pattern having a plurality of first scale patterns arranged in a first direction. The second semiconductor device is mounted over the first semiconductor device and includes a second alignment pattern having a plurality of second scale patterns arranged in a second direction parallel to the first direction, and a scale pitch of the first scale patterns is different from a scale pitch of the second scale patterns.

A semiconductor package includes; a first redistribution structure including first redistribution conductors, a semiconductor chip on the first redistribution structure and including connection pads electrically connecting the first redistribution conductors, a connection conductor on the first redistribution structure, laterally spaced apart from the semiconductor chip, and electrically connected to the first redistribution conductors, an encapsulant on the first redistribution structure and sealing the semiconductor chip and at least a portion of the connection conductor, a barrier layer extending along an upper surface of the encapsulant, and a second redistribution conductor on the barrier layer and penetrating the barrier layer to contact the connection conductor.

A package comprises at least one first device die, and a redistribution line (RDL) structure having the at least one first device die bonded thereto. The RDL structure comprises a plurality of dielectric layers, and a plurality of RDLs formed through the plurality of dielectric layers. A trench is defined proximate to axial edges of the RDL structure through each of the plurality of dielectric layers. The trench prevents damage to portions of the RDL structure located axially inwards of the trench.

A semiconductor package includes a redistribution portion including an insulating layer, a redistribution layer, and a redistribution via, an under-bump metallurgy (UBM) layer below the redistribution portion and including a UBM pad on a lower surface of the redistribution portion and a UBM via on the UBM pad to penetrate through the insulating layer, a semiconductor chip on an upper surface of the redistribution portion and electrically connected to the redistribution layer, an adhesive layer between the UBM layer and the insulating layer and including a conductive material, and a connection bump below the UBM pad and connected to the UBM layer. The UBM pad has a first diameter, and the UBM via has a second diameter, less than the first diameter, and an upper surface of the UBM pad is located on the same level as, or a level lower than, a lower surface of the insulating layer.

Disclosed are semiconductor packages and their fabrication methods. The semiconductor package includes a redistribution substrate that includes an organic dielectric layer and a metal pattern in the organic dielectric layer, and a semiconductor chip on the redistribution substrate. The organic dielectric layer has a maximum absorbance equal to or greater than about 0.04 at a first wavelength range, and a fluorescence intensity equal to or greater than about 4×10.sup.3 at the first wavelength range. The first wavelength range is about 450 nm to about 650 nm.

A power device assembly includes a heat-generating device, one or more porous bonding layers, and one or more cap layers. The one or more porous bonding layers are formed on a surface of the heat-generating device and define a plurality of embedded vapor channels. The one or more cap layers are engaged with a porous bonding layer of the one or more porous bonding layers opposite the heat-generating device. The one or more cap layer comprise a plurality of liquid feed channels for feeding cooling fluid to the heat-generating device via the porous bonding layer.

A power device for surface mounting has a leadframe including a die-attach support and at least one first lead and one second lead. A die, of semiconductor material, is bonded to the die-attach support, and a package, of insulating material and parallelepipedal shape, surrounds the die and at least in part the die-attach support and has a package height. The first and second leads have outer portions extending outside the package, from two opposite lateral surfaces of the package. The outer portions of the leads have lead heights greater than the package height, extend throughout the height of the package, and have respective portions projecting from the first base.

The present disclosure provides a semiconductor chip having a non-through plug contour (buried alignment mark) for stacking aligmnent and a multi-chip semiconductor device employing thereof, and to a method for manufacturing same. In some embodiments, the semiconductor chip includes a semiconductor substrate having a first side and a second side, a conductive through plug extending through the semiconductor substrate from the first side to the second side, and a non-through plug extending from the first side to an internal plane of the semiconductor substrate without extending through the second side.