A semiconductor package may include a first substrate and a second substrate. Socket bumps may be disposed on the first substrate to provide insertion grooves within the socket bumps. Plug bumps may be disposed on the second substrate. The plug bumps may be configured for insertion into the insertion grooves of the socket bumps and may electrically connect to the socket bumps. Related memory cards and electronic systems may also be provided.

A package includes a chip, a wire, a mold layer and a redistribution layer. The chip includes a conductive pad. The wire is bonded to the conductive pad of the chip. The mold layer surrounds the first chip and the wire. The redistribution layer is disposed on the mold layer and contacts an exposed portion of the wire.

A plug-in type power module includes a power unit and a heat-transfer unit vertically disposed on the power unit and extending outwardly away from two sides of the power unit. A first ceramic layer is disposed between the power unit and the heat-transfer unit. Therefore, heat generated by the power unit can be transferred from the first ceramic layer to the heat-transfer unit to increase the speed of heat dissipation. A subsystem having the plug-in type power module is also provided.

The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein a first microelectronic device having through-silicon vias may be stacked with a second microelectronic device and used in a bumpless build-up layer package.

A semiconductor module is disclosed. The semiconductor module may include a housing having a sidewall portion, a housing support plate coupled to a bottom surface of the sidewall portion such that the housing support plate and the sidewall portion define an interior space of the housing of the semiconductor module, and a semiconductor device disposed within the interior space and fixedly coupled to the housing. The semiconductor module may further include a cover member fixedly attached to a top surface of the sidewall portion such that the cover member, the housing and the housing support plate form a protective enclosure for the semiconductor device.

An integrated circuit package and a method of forming the same are provided. A method includes stacking a plurality of integrated circuit dies on a wafer to form a die stack. A bonding process is performed on the die stack. The bonding process mechanically and electrically connects adjacent integrated circuit dies of the die stack to each other. A dam structure is formed over the wafer. The dam structure surrounds the die stack. A first encapsulant is formed over the wafer and between the die stack and the dam structure. The first encapsulant fills gaps between the adjacent integrated circuit dies of the die stack. A second encapsulant is formed over the wafer. The second encapsulant surrounds the die stack, the first encapsulant and the dam structure.

The present technology relates to a semiconductor apparatus, a production method, and an electronic apparatus that enable semiconductor apparatuses to be laminated and the laminated semiconductor apparatuses to be identified. A semiconductor apparatus that is laminated and integrated with a plurality of semiconductor apparatuses, includes a first penetrating electrode for connecting with the other semiconductor apparatuses and a second penetrating electrode that connects the first penetrating electrode and an internal device, the second penetrating electrode being arranged at a position that differs for each of the laminated semiconductor apparatuses. The second penetrating electrode indicates a lamination position at a time of lamination. An address of each of the laminated semiconductor apparatuses in a lamination direction is identified by writing using external signals after lamination. The present technology is applicable to a memory chip and an FPGA chip.

A method includes forming an under bump metallization (UBM) layer over a dielectric layer, forming a redistribution structure over the UBM layer, disposing a semiconductor device over the redistribution structure, removing a portion of the dielectric layer to form an opening to expose the UBM layer, and forming a conductive bump in the opening such that the conductive bump is coupled to the UBM layer.

A press-pack semiconductor fixture 200 includes a housing defining an interior passage. A first conductor and a second conductor are mechanically coupled with the housing. The mechanical coupling of the first conductor and the second conductor with the housing is effective to apply a clamping force to a press pack semiconductor. A number of apertures or openings are provided in the housing, the first conductor, and the second conductor to permit fluidic flow 290 between the interior passage 239 and spaces or structures exterior to the housing.

A semiconductor device and a fabricating method of semiconductor device are disclosed. The semiconductor device comprises: a substrate having a bonding pad on a surface of the substrate; at least two semiconductor components each having a first surface and a second surface opposite the first surface, the semiconductor components stacked on top of each other on the surface of the substrate via a layer of component attach material attached on the second surface of the respective semiconductor component; an integral through via hole extending completely through the semiconductor components and the layers of component attach material and having a substantially uniform diameter along an extending direction of the integral through via hole aligned with the bonding pad on the surface of the substrate, and a continuous conductive material filled in the integral through via hole and in physical and electrical contact with the bonding pad of the substrate.