A semiconductor device is provided that includes a temperature sensing function that accurately senses a temperature. The semiconductor device includes a first semiconductor layer on a semiconductor substrate, and a temperature sensor. The temperature sensor includes: a sensing-body region of a second conductivity type that is disposed in the first semiconductor layer; a first region of a first conductivity type, and a second region of the first conductivity type that are arranged in the sensing-body region and are apart from each other; and a third region of the second conductivity type that is in the sensing-body region and is between the first region and the second region. A concentration of a first conductivity type impurity in the temperature-sensing conductive layer is higher than a concentration of a first conductivity type impurity in the drift region.

Integrated circuit dies, systems, devices, and techniques, are described herein related to embedding a thermal solution into an integrated circuit die to heat the integrated circuit die when deployed in sub-zero environments, techniques for operating the thermal solution in a system, and techniques for fabricating the embedded thermal solution. The thermal solution includes a resistive heating element having the same material and substantially coplanar with components of devices of the integrated circuit die.

Structures for an array of non-volatile memory cells and methods of forming a structure for an array of non-volatile memory cells. An active region of a substrate includes a first section having a side edge and a second section extending laterally from the side edge. The first section of the active region has a first length dimension in a direction parallel to the first side edge. The second section has a second length dimension in the direction parallel to the first side edge. The second length dimension is less than the first length dimension. A fin is positioned on the substrate in the second section of the active region. A gate structure extends over the fin and the second section of the active region.

Methods, systems, and apparatus, including an integrated circuit (IC) with a ring-shaped hot spot area. In one aspect, an IC includes a first area along an outside perimeter of a surface of the IC. The first area defines a first inner perimeter. The IC includes a second area that includes a center of the IC and that includes a first set of components. The second area defines a first outer. The IC includes a ring-shaped hot spot area between the first area and the second area. The ring-shaped hot spot area defines a ring outer perimeter that is juxtaposed with the first inner perimeter. The ring-shaped hot spot area defines a ring inner perimeter that is juxtaposed with the first outer perimeter. The ring-shaped hot spot area includes a second set of components that produce more heat than the first set of components.

A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.

A thin film resistor is provided, and a resistance layer of the thin film resistor is a patternized mesh. The mesh density of the mesh resistance layer increases from center to both ends of the film resistor. The temperature peak is shifted from the center to both ends of the film resistor. Therefore, the heat can be quickly dissipated via the electrodes.

Structures for an array of non-volatile memory cells and methods of forming a structure for an array of non-volatile memory cells. An active region of a substrate includes a first section having a side edge and a second section extending laterally from the side edge. The first section of the active region has a first length dimension in a direction parallel to the first side edge. The second section has a second length dimension in the direction parallel to the first side edge. The second length dimension is less than the first length dimension. A fin is positioned on the substrate in the second section of the active region. A gate structure extends over the fin and the second section of the active region.

A semiconductor device including a transistor section and a diode section, the semiconductor device having: a temperature sensing section; a neighboring transistor section adjacent to the temperature sensing section; a neighboring diode section adjacent to the temperature sensing section; and a first non-neighboring diode section that is not adjacent to the temperature sensing section, wherein the first non-neighboring diode section has a pattern different from the pattern of the neighboring diode section in the top view is provided.

A bandgap voltage reference circuit includes first and second transistors (e.g., 3-terminal BJTs or diode-connected BJTs), and a PTAT element (e.g., resistance or capacitance). The first transistor is at a first die location, and operates with a first base-emitter voltage. The second transistor is at a second die location, and operates with a second base-emitter voltage. Each of the first and second transistors may include multiple individual parallel-connected transistors. The PTAT element is operatively coupled to the first and second transistors such that a voltage difference between the first and second base-emitter voltages drops across the PTAT element. The first and second locations are separated by a distance (e.g., 1.5% or more of die length, or such that the respective centroids of the first and second transistor are spaced from one another). Such spatial distribution helps mitigate voltage shift induced by mechanical stress, and is insensitive to process variation.

Methods, systems, and apparatus, including an integrated circuit (IC) with a ring-shaped hot spot area. In one aspect, an IC includes a first area along an outside perimeter of a surface of the IC. The first area defines a first inner perimeter. The IC includes a second area that includes a center of the IC and that includes a first set of components. The second area defines a first outer. The IC includes a ring-shaped hot spot area between the first area and the second area. The ring-shaped hot spot area defines a ring outer perimeter that is juxtaposed with the first inner perimeter. The ring-shaped hot spot area defines a ring inner perimeter that is juxtaposed with the first outer perimeter. The ring-shaped hot spot area includes a second set of components that produce more heat than the first set of components.