A semiconductor device includes a transistor stack. The transistor stack has a plurality of transistors that are stacked over a substrate. Each of the plurality of transistors includes a channel region stacked over the substrate and extending in a direction parallel to the substrate, a gate structure stacked over the substrate and surrounding the channel region of each of the plurality of transistors, and source/drain (S/D) regions stacked over the substrate and further positioned at two ends of the channel region of each of the plurality of transistors. The semiconductor device also includes one or more conductive planes formed over the substrate. The one or more conductive planes are positioned adjacent to the transistor stack, span a height of the transistor stack, and are electrically coupled to the transistor stack.

III-nitride materials are described herein, including material structures comprising III-nitride material regions (e.g., gallium nitride material regions). In certain cases, the material structures also comprise substrates having relatively high electrical conductivities. Certain embodiments include one or more features that reduce the degree to which thermal runaway occurs, which can enhance device performance including at elevated flange temperatures. Some embodiments include one or more features that reduce the degree of capacitive coupling exhibited during operation. For example, in some embodiments, relatively thick III-nitride material regions and/or relatively small ohmic contacts are employed.

We describe herein a high voltage semiconductor device comprising a power semiconductor device portion (100) and a temperature sensing device portion (185). The temperature sensing device portion comprises: an anode region (140), a cathode region (150), a body region (160) in which the anode region and the cathode region are formed. The temperature sensing device portion also comprises a semiconductor isolation region (165) in which the body region is formed, the semiconductor isolation region having an opposite conductivity type to the body region, the semiconductor isolation region being formed between the power semiconductor device portion and the temperature sensing device portion.

Provided herein are semiconductor dies including multiple controllers for operating over an extended temperature range. In certain embodiments, a semiconductor die includes multiple circuit modules, a temperature sensor that generates a detected temperature signal, an interface that communicates with an external host, a primary controller coupled to the interface and operable to control the circuit modules, and a secondary controller coupled to the interface. In response to the detected temperature signal indicating that the temperature of the semiconductor die exceeds a threshold temperature, the primary controller enables the secondary controller, which in turn disables the primary controller and at least a portion of the plurality of circuit modules to reduce heat dissipation.

A 3D semiconductor device including: a first level, where the first level includes a first layer and first transistors, and where the first level includes a second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer, the third layer including second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; a plurality of connection paths, where the plurality of connection paths provides connections from a plurality of the first transistors to a plurality of the second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions, where the bonded includes metal to metal bond regions, where the second level includes at least one memory array, where the third layer includes crystalline silicon; and where the second level includes at least one SerDes circuit.

A temperature-sensing device configured to monitor a temperature includes: a first conductive line; a second conductive line, wherein the first and second conductive lines have respective different cross-sectional dimensions; a sensing circuit, coupled to the first and second conductive lines, and configured to determine a logic state of an output signal based on a difference between respective signal levels present on the first and second conductive lines; and a control circuit, coupled to the sensing circuit, and configured to determine whether the monitored temperature is above or below a pre-defined threshold temperature based on the determined logic state.

A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.

III-nitride materials are described herein, including material structures comprising III-nitride material regions (e.g., gallium nitride material regions). In certain cases, the material structures also comprise substrates having relatively high electrical conductivities. Certain embodiments include one or more features that reduce the degree to which thermal runaway occurs, which can enhance device performance including at elevated flange temperatures. Some embodiments include one or more features that reduce the degree of capacitive coupling exhibited during operation. For example, in some embodiments, relatively thick III-nitride material regions and/or relatively small ohmic contacts are employed.

A semiconductor device is provided. The semiconductor device includes a transistor stack having a plurality of transistor pairs that are stacked over a substrate. Each transistor pair of the plurality of transistor pairs includes a n-type transistor and a p-type transistor that are stacked over one another. The plurality of transistor pairs have a plurality of gate electrodes that are stacked over the substrate and electrically coupled to gate structures of the plurality of transistor pairs, and a plurality of source/drain (S/D) local interconnects that are stacked over the substrate and electrically coupled to source regions and drain regions of the plurality of transistor pairs. The semiconductor device further includes one or more conductive planes formed over the substrate. The one or more conductive planes are positioned adjacent to the transistor stack, span a height of the transistor stack and are electrically coupled to the transistor stack.

A 3D semiconductor device including: a first level, where the first level includes a first layer and first transistors, and where the first level includes a second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer, the third layer including second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; a plurality of connection paths, where the plurality of connection paths provides connections from a plurality of the first transistors to a plurality of the second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions, where the bonded includes metal to metal bond regions, where the second level includes at least one memory array, where the third layer includes crystalline silicon; and where the second level includes at least one SerDes circuit.