A semiconductor device includes a bottom tier including a plurality of first vertical transistors and at least one contact disposed on a first inverter gate. The device further includes a top tier including a plurality of second vertical transistors and a second inverter gate, and a monolithic inter-tier via (MIV) that lands on the at least one contact via the second inverter gate to create a three-dimensional monolithic vertical transistor memory cell with unified inter-tier cross-couple.

III-nitride materials are described herein, including material structures comprising III-nitride material regions (e.g., gallium nitride material regions). In certain cases, the material structures also comprise substrates having relatively high electrical conductivities. Certain embodiments include one or more features that reduce the degree to which thermal runaway occurs, which can enhance device performance including at elevated flange temperatures. Some embodiments include one or more features that reduce the degree of capacitive coupling exhibited during operation. For example, in some embodiments, relatively thick III-nitride material regions and/or relatively small ohmic contacts are employed.

A semiconductor device includes a first gate electrode, a plurality of first source electrodes, a second gate electrode, and a plurality of second source electrodes. The first gate electrode is arranged with no other electrode between the first gate electrode and a first short side of the semiconductor substrate. The plurality of first source electrodes include a plurality of approximately rectangular first source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate. The second gate electrode is arranged with no other electrode between the second gate electrode and a second short side of the semiconductor substrate. The plurality of second source electrodes include a plurality of approximately rectangular second source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate.

A semiconductor device and a method for forming the semiconductor device. The semiconductor device includes: a unipolar component at least including a first epitaxial layer and a first substrate; and a bypass component at least including a second epitaxial layer and a second substrate; the unipolar component and the bypass component are connected in parallel; a difference of a thickness of the unipolar component and a thickness of the bypass component is lower than or equal to a predetermined value.

An electrostatic discharge (ESD) protection device includes a substrate including a device region and an ESD protection structure formed on the substrate in the device region. The device region includes a center region and edge regions separated by the center region, while the ESD protection structure includes a plurality of gate structures. The ESD protection device also includes a dielectric layer formed to cover the plurality of gate structures and a plurality of heat dissipation structures formed on the dielectric layer with each heat dissipation structure aligned with a corresponding gate structure along a direction perpendicular to a surface of the substrate. The area size of each heat dissipation structure aligned with a corresponding gate structure in the center region is larger than the area size of each heat dissipation structure aligned with a corresponding gate structure in the edge region.

A semiconductor device includes transistor cells in a semiconductor portion, wherein the transistor cells are electrically connected to a gate metallization, a source electrode and a drain electrode. In one example, the semiconductor device further includes a doped region in the semiconductor portion. The doped region is electrically connected to the source electrode. A resistance of the doped region has a negative temperature coefficient. An interlayer dielectric separates the gate metallization from the doped region. A drain structure in the semiconductor portion electrically connects the transistor cells with the drain electrode and forms a pn junction with the doped region.

Semiconductor structures and devices in III-nitride materials are described herein, including material structures comprising III-nitride material regions (e.g., gallium nitride material regions). In certain cases, the material structures comprise substrates having relatively high electrical conductivities. In other cases, the material structures comprise substrates having relatively high resistivities. Certain embodiments include one or more features that reduce the degree to which thermal runaway occurs, which can enhance device performance including at elevated flange temperatures. Some embodiments include one or more features that reduce the degree of capacitive coupling exhibited during operation. For example, in some embodiments, relatively thick III-nitride material regions and/or relatively small ohmic contacts are employed.

A semiconductor device that is equipped with a MOSFET with a Zener diode embedded and capable of achieving both improvement in the surge resistance and the low on-resistance of the MOSFET is provided. The semiconductor device equipped with a MOSFET with a Zener diode embedded includes an active region in which the MOSFET operates, and a peripheral region that is disposed outside of the active region and holds a withstand voltage of a chip peripheral portion, in which the active region includes a first region including a chip central portion and a second region disposed outside of the first region, and a withstand voltage of the first region is lower than a withstand voltage of the second region and a withstand voltage of the peripheral region.

A power semiconductor device includes a power transistor arranged in a power device region of a semiconductor substrate. The power semiconductor device further includes a first circuit arranged in a first circuit region of the semiconductor substrate. The power semiconductor device further includes a second circuit arranged in a second circuit region of the semiconductor substrate. The first circuit region is arranged at a first edge of the semiconductor substrate. The second circuit region is arranged at a second edge of the semiconductor substrate. The power device region is arranged between the first circuit region and the second circuit region.

A method includes identifying fingers of a first device and fingers of a second device. The method includes grouping the fingers of the first device into a first finger group and a second finger group, wherein the first finger group is electrically connected to the second finger group. The method further includes positioning the first finger group extends across a first doped region. The method further includes positioning the second finger group extends across a second doped region, wherein the second doped region has a same dopant type as the first doped region. The method further includes grouping the fingers of the second device into a third finger group and a fourth finger group, wherein the third finger group is electrically connected to the fourth finger group. The method further includes positioning the third finger group and the fourth finger group extending across the second doped region.