Disclosed herein is an electronic device including a substrate having a conductive area formed thereon. A first molding level is stacked on the substrate. A die is formed on the substrate and within the first molding level. A second molding level is stacked on the first molding level. At least one passive component is within the second molding level. A conductive structure extends between the second molding level and the substrate and electrically couples the at least one passive component to the conductive area.

A semiconductor device that can hold ESD immunity with a simple configuration is provided.

The semiconductor device includes a power supply wiring, a ground wiring, an input circuit coupled between the power supply wiring and the ground wiring, an input pad which is coupled with the input circuit and to which a negative voltage lower than a voltage supplied to the ground wiring can be inputted, a plurality of first diodes provided between the ground wiring and the input pad, and a second diode provided between the input pad and the power supply wiring. A reverse bias breakdown voltage of the second diode is greater than a reverse bias breakdown voltage of each of the first diodes.

Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). For example, in some embodiments, an IC package support may include: a first conductive structure in a dielectric material; a second conductive structure in the dielectric material; and a material in contact with the first conductive structure and the second conductive structure, wherein the material includes a polymer, and the material is different from the dielectric material. The material may act as a dielectric material below a trigger voltage, and as a conductive material above the trigger voltage.

A semiconductor device includes a semiconductor layer that has a transistor structure including a p type source region, a p type drain region, an n type body region between the p type source region and the p type drain region, and a gate electrode facing the n type body region and a voltage-regulator diode that is disposed at the semiconductor layer and that has an n type portion connected to the p type source region and a p type portion connected to the gate electrode, in which the transistor structure and the voltage-regulator diode are unified into a single-chip configuration.

A protective circuit includes a non-linear element which includes a gate electrode, a gate insulating layer covering the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode over the gate insulating layer, a channel protective layer overlapping with a channel formation region of the first oxide semiconductor layer, and a pair of a first wiring layer and a second wiring layer whose end portions overlap with the gate electrode over the channel protective layer and in which a conductive layer and a second oxide semiconductor layer are stacked. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be reduced and the characteristics of the non-linear element can be improved.

A block of logic gates has MOS transistors whose body terminals are connected with a body voltage rail and whose source terminals are connected with a logic reference voltage rail. The logic reference voltage rail is connected to the body voltage rail via a resistor. The resistor creates a negative feedback loop for leakage currents that stabilizes a reverse body bias voltage and reduces the influence of temperature, voltage, and process variations.

The block may be NMOS, PMOS, or CMOS. In the case of CMOS, there are two body voltage rails, powered by a voltage source, two logic reference voltage rails, and two resistors. The reverse body bias voltages over the two resistors may be stabilized by decoupling capacitors. The two resistors may be trimmable. The resistors may be calibrated such that leakage currents are at a minimum value and the logic gates can switch just fast enough.

A semiconductor component, for example an integrated circuit chip, including a semiconductor substrate having active devices at the front side thereof and I/O terminals at the back side of the component, is provided. In one aspect, the terminals are connected to the active devices through TSV connections and buried rails in an area of the substrate that is separate from the area in which the active devices are located. The I/O TSV connections are located in a floating well of the substrate that is separated from the rest of the substrate by a second well formed of material of the opposite conductivity type compared to the material of the floating well. The second well includes at least one contact configured to be coupled to a voltage that is suitable for reverse-biasing the junction between the floating well and the second well. A small capacitance is placed in series with the large parasitic capacitance generated by a thin dielectric liner that isolates the I/O TSVs and I/O rails from the substrate, thereby mitigating the negative effect of the large parasitic capacitance. Additional contacts and conductors can be provided which are configured to create an ESD protection circuit for protecting the I/O TSVs and the I/O rails from electrostatic discharges.

A circuit device includes core circuitry. The circuit device further includes a first plurality of guard rings having a first dopant type, wherein the first plurality of guard rings is around a periphery of the core circuitry. The circuit device further includes a second plurality of guard rings having a second dopant type, wherein the second dopant type is opposite to the first dopant type, and at least one guard ring of the second plurality of guard rings is around a periphery of at least one guard ring of the first plurality of guard rings.

Multiple termination impedance values are provided in a switchable termination circuit so as to accommodate multiple transmission line characteristics. In one example, a termination matching circuit includes first and second nodes, a series interconnection of a first switch and a first impedance coupled between the first and second nodes, and another series interconnection of a second switch and a second impedance coupled between the first and second nodes. First and second control circuits respectively control the first and second switches such that a selectable impedance is provided between the first and second nodes through selective activation of the first and second switch devices by the first and second control circuits. In another example, additional nodes and resistors are provided to provide further termination impedance values.

A layout structure of an ESD protection semiconductor device includes a substrate, a first doped region, a pair of second doped regions, a pair of third doped regions, at least a first gate structure formed within the first doped region, and a drain region and a first source region formed at two sides of the first gate structure. The substrate, the first doped region and the third doped regions include a first conductivity type. The second doped regions, the drain region and the first source region include a second conductivity type complementary to the first conductivity type. The first doped region includes a pair of lateral portions and a pair of vertical portions. The pair of second doped regions is formed under the pair of lateral portions, and the pair of third doped regions is formed under the pair of vertical portions.