On a single-crystal semiconductor substrate with an upper surface including a first direction in which an inverted mesa step extends and a second direction in which a forward mesa step extends in response to anisotropic etching in which an etching rate depends on crystal plane orientation, a bipolar transistor including a collector layer, a base layer, and an emitter layer that are epitaxially grown, and a base wire connected to the base layer are arranged. A step is provided at an edge of the base layer, and the base wire is extended from inside to outside of the base layer in a direction intersecting the first direction in a plan view. An intersection of the edge of the base layer and the base wire has a disconnection prevention structure that makes it difficult for step-caused disconnection of the base wire to occur.

An integrated circuit includes a semiconductor substrate, first and second doping regions in the substrate, a first insulating layer on a first surface of the semiconductor substrate, the first insulating layer having first and second openings above the first and second doping regions, a polysilicon layer on the first insulating layer, the polysilicon layer having first and second openings above the first and second openings of the first insulating layer, a second insulating layer on the polysilicon layer and having first and second openings above the first and second openings of the polysilicon layer, a first contact element disposed in the first openings, a second contact element disposed in the second openings, the first and second contact elements being in contact with the first and second doping regions.

An integrated circuit includes a semiconductor substrate, first and second doping regions in the substrate, a first insulating layer on a first surface of the semiconductor substrate, the first insulating layer having first and second openings above the first and second doping regions, a polysilicon layer on the first insulating layer, the polysilicon layer having first and second openings above the first and second openings of the first insulating layer, a second insulating layer on the polysilicon layer and having first and second openings above the first and second openings of the polysilicon layer, a first contact element disposed in the first openings, a second contact element disposed in the second openings, the first and second contact elements being in contact with the first and second doping regions.

A semiconductor device includes a first semiconductor pattern doped with first impurities on a substrate, a first channel pattern on the first semiconductor pattern, second semiconductor patterns doped with second impurities contacting upper edge surfaces, respectively, of the first channel pattern, and a first gate structure surrounding at least a portion of a sidewall of the first channel pattern.

A transient voltage suppression device includes a lightly-doped semiconductor structure, a first doped well, a first heavily-doped area, a first buried area, and a second heavily-doped area. The lightly-doped semiconductor structure has a first conductivity type. The first doped well has a second conductivity type and is formed in the lightly-doped semiconductor structure. The first heavily-doped area has the second conductivity type and is formed in the first doped well. The first buried area has the first conductivity type and is formed in the lightly-doped semiconductor structure and under the first doped well, and the first buried area is adjacent to the first doped well. The second heavily-doped area has the second conductivity type and is formed in the lightly-doped semiconductor structure.

A transient voltage suppression device includes a lightly-doped semiconductor structure, a first doped well, a first heavily-doped area, a first buried area, and a second heavily-doped area. The lightly-doped semiconductor structure has a first conductivity type. The first doped well has a second conductivity type and is formed in the lightly-doped semiconductor structure. The first heavily-doped area has the second conductivity type and is formed in the first doped well. The first buried area has the first conductivity type and is formed in the lightly-doped semiconductor structure and under the first doped well, and the first buried area is adjacent to the first doped well. The second heavily-doped area has the second conductivity type and is formed in the lightly-doped semiconductor structure.

A semiconductor device has a semiconductor substrate, and multiple first bipolar transistors on the first primary surface side of the semiconductor substrate. The first bipolar transistors have a first height between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. The semiconductor device further has at least one second bipolar transistor on the first primary surface side of the semiconductor substrate. The second bipolar transistor have a second height, greater than the first height, between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. Also, the semiconductor has a first bump stretching over the multiple first bipolar transistors and the at least one second bipolar transistor.

A current source includes a substrate, a base region of a first doping type formed in the substrate, an emitter region of a second doping type formed in the substrate and surrounding the base region, a first collector region of the second doping type formed in the base region, and at least one second collector region of the second doping type formed in the base region, wherein the emitter region includes a deep-well portion and an extending portion, the deep-well portion situated beneath the base region, the extending portion laterally surrounding the base region, the extending portion joined at its bottom to the deep-well portion, the extending portion being flush at its top with a top surface of the substrate. A method of forming the current source is also disclosed.

A compound semiconductor device comprises a heterojunction bipolar transistor including a plurality of unit transistors, a capacitor electrically connected between a RF input wire and a base wire for each unit transistor of the unit transistors, and a bump electrically connected to emitters of the unit transistors. The unit transistors are arranged in a first direction. The bump is disposed above the emitters of the unit transistors while extending in the first direction. The transistors include first and second unit transistors, the respective emitters of the first and second unit transistors being disposed on first and second sides, respectively, of a second direction, perpendicular to the first direction, with respect to a center line of the bump extending in the first direction. The capacitor is not covered by the bump, and respective lengths of the respective base wires connected respectively to the first and second unit transistors are different.

Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a substrate having a p-type well or an n-type well, a first base portion over the p-type well, a second base portion over the n-type well, a first plurality of channel members over the first base portion, a second plurality of channel members over the second base portion, an isolation feature disposed between the first base portion and the second base portion, and a deep isolation structure in the substrate disposed below the isolation feature.