At least one unit transistor is arranged over a substrate. A first wiring as a path of current that flows to each unit transistor is arranged over the at least one unit transistor. An inorganic insulation film is arranged over the first wiring. At least one first opening overlapping a partial region of the first wiring in a plan view is provided in the inorganic insulation film. An organic insulation film is arranged over the inorganic insulation film. A second wiring coupled to the first wiring through the first opening is arranged over the organic insulation film and the inorganic insulation film. In a plan view, a region in which the organic insulation film is not arranged is provided outside a region in which the first wiring is arranged. The second wiring is in contact with the inorganic insulation film outside the region in which the first wiring is arranged.

On a single-crystal semiconductor substrate with an upper surface including a first direction in which an inverted mesa step extends and a second direction in which a forward mesa step extends in response to anisotropic etching in which an etching rate depends on crystal plane orientation, a bipolar transistor including a collector layer, a base layer, and an emitter layer that are epitaxially grown, and a base wire connected to the base layer are arranged. A step is provided at an edge of the base layer, and the base wire is extended from inside to outside of the base layer in a direction intersecting the first direction in a plan view. An intersection of the edge of the base layer and the base wire has a disconnection prevention structure that makes it difficult for step-caused disconnection of the base wire to occur.

Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A first heterojunction bipolar transistor includes a first emitter, a first collector, and a first base layer having a portion positioned between the first emitter and the first collector. A second heterojunction bipolar transistor includes a second emitter, a second collector, and a second base layer having a portion positioned between the second emitter and the second collector. The first and second base layers each comprise silicon-germanium, the first base layer includes a first germanium profile, and the second base layer includes a second germanium profile that is identical to the first germanium profile.

One illustrative device disclosed herein includes a semiconductor substrate, a bipolar junction transistor (BJT) device that comprises a collector, a base and an emitter, at least one piezoelectric structure comprising a piezoelectric material positioned adjacent the BJT device, and at least first and second conductive contact structures that are conductively coupled to the piezoelectric structure.

A half-bridge circuit includes a low-side transistor and a high-side transistor each having a load path and a control terminal, and a high-side drive circuit having a level shifter with a level shifter transistor. The low-side transistor and the level shifter transistor are integrated in a common semiconductor body.

A transient voltage suppressor (TVS) device uses a punch-through silicon controlled rectifier (SCR) structure for the low-side steering diode where the punch-through SCR structure realizes low capacitance at the protected node. In some embodiments, the punch-through silicon controlled rectifier of the low-side steering diode includes a first doped region formed in a first epitaxial layer, a first well formed spaced apart from the first doped region where the first well is not biased to any electrical potential, and a second doped region formed in the first well. The first doped region, the first epitaxial layer, the first well and the second doped region form the punch-through silicon controlled rectifier, with the first doped region forming the anode and the second doped region forming the cathode of the punch-through silicon controlled rectifier.

A semiconductor device includes a semiconductor element including a bipolar transistor disposed on a compound semiconductor substrate, a collector electrode, a base electrode, and an emitter electrode, the bipolar transistor including a collector layer, a base layer, and an emitter layer, the collector electrode being in contact with the collector layer, the base electrode being in contact with the base layer, the emitter electrode being in contact with the emitter layer; a protective layer disposed on one surface of the semiconductor element; an emitter redistribution layer electrically connected to the emitter electrode via a contact hole in the protective layer; and a stress-relieving layer disposed between the emitter redistribution layer and the emitter layer in a direction perpendicular to a surface of the compound semiconductor substrate.

An integrated circuit includes a plurality of first n-type regions and a plurality of second n-type regions that each intersect a surface of a substrate. The first n-type regions are arranged in a first linear array within a first n-well and a second linear array within a second n-well. The first and second n-wells are each located within and separated by a first p-type region. The second n-type regions are located within and separated by a second p-type region. An n-type trench region is located between the first and second p-type regions. The n-type trench region extends into the substrate toward an n-type buried layer that extends under the first p-type region and the second p-type region.

A semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor (HBT) includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors through respective overlying conductor filled via openings that overlap in a plan view with a width portion of the bump. The semiconductor device reduces heat resistance in an HBT cell by satisfying two conditions, the first of which is related to specific sizing and positioning of a width portion of the overlying via opening relative to the width portion of the bump, and the second of which is related to positioning the base electrode entirely within a specific region of the width portion of the overlapping overlying via opening.

The present invention is directed to a semiconductor chip comprising a high voltage device and a low voltage device disposed thereon. The chip may be formed in several different configurations. For example, the semiconductor chip may include a NPN bipolar transistor, PNP bipolar transistor, a diode, an N channel DMOS transistor and the like. the first doped well being configured as a base of the DMOS transistor, a P channel DMOS transistor and the like. These and other embodiments are described in further detail below.