Provided is a semiconductor device with a reduced variation in temperature among a plurality of unit transistors. A semiconductor device includes: a semiconductor substrate; and a transistor group including at least one column in which a plurality of unit transistors are aligned and arranged along a first axis on the semiconductor substrate. A first column of the at least one column includes: a first group of transistors including two of the unit transistors that are adjacent to each other with a first distance therebetween, and a second group of transistors including two of the unit transistors that are adjacent to each other with a second distance therebetween, the first group of transistors is disposed at a position closer to a center of the first column along the first axis than the second group of transistors, and the first distance is larger than the second distance.

Provided is a semiconductor device with a reduced variation in temperature among a plurality of unit transistors. A semiconductor device includes: a semiconductor substrate; and a transistor group including at least one column in which a plurality of unit transistors are aligned and arranged along a first axis on the semiconductor substrate. A first column of the at least one column includes: a first group of transistors including two of the unit transistors that are adjacent to each other with a first distance therebetween, and a second group of transistors including two of the unit transistors that are adjacent to each other with a second distance therebetween, the first group of transistors is disposed at a position closer to a center of the first column along the first axis than the second group of transistors, and the first distance is larger than the second distance.

An embodiment of a semiconductor device comprises a transistor cell array in a semiconductor body. The transistor cell array comprises transistor cell units. Each of the transistor cell units comprises a control terminal and first and second load terminals, respectively. The transistor cell units are electrically connected in parallel, and the control terminals of the transistor cells units are electrically connected. A first group of the transistor cell units includes a first threshold voltage. A second group of the transistor cell units includes a second threshold voltage larger than the first threshold voltage. A channel width of a transistor cell unit of the first group is smaller than a channel width of a transistor cell unit of the second group.

An embodiment of a semiconductor device comprises a transistor cell array in a semiconductor body. The transistor cell array comprises transistor cell units. Each of the transistor cell units comprises a control terminal and first and second load terminals, respectively. The transistor cell units are electrically connected in parallel, and the control terminals of the transistor cells units are electrically connected. A first group of the transistor cell units includes a first threshold voltage. A second group of the transistor cell units includes a second threshold voltage larger than the first threshold voltage. A channel width of a transistor cell unit of the first group is smaller than a channel width of a transistor cell unit of the second group.

Semiconductor structure including germanium-on-insulator lateral bipolar junction transistors and methods of fabricating the same generally include formation of a silicon passivation layer at an interface between the insulator layer and a germanium layer.

A compound semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors. The plurality of unit transistors are arranged in a first direction. The bump is disposed above the emitters of the plurality of unit transistors while extending in the first direction. The emitter of at least one of the plurality of unit transistors is displaced from a center line of the bump in the first direction toward a first side of a second direction which is perpendicular to the first direction. The emitter of at least another one of the plurality of unit transistors is displaced from the center line of the bump in the first direction toward a second side of the second direction.

An ESD protection device is fabricated in a semiconductor substrate that includes a semiconductor layer having a first conductivity type. A first well implantation procedure implants dopant of a second conductivity type in the semiconductor layer to form inner and outer sinker regions. The inner sinker region is configured to establish a common collector region of first and second bipolar transistor devices. A second well implantation procedure implants dopant of the first conductivity type in the semiconductor layer to form respective base regions of the first and second bipolar transistor devices. Conduction of the first bipolar transistor device is triggered by breakdown between the inner sinker region and the base region of the first bipolar transistor device. Conduction of the second bipolar transistor device is triggered by breakdown between the outer sinker region and the base region of the second bipolar transistor device.

An ESD protection device is fabricated in a semiconductor substrate that includes a semiconductor layer having a first conductivity type. A first well implantation procedure implants dopant of a second conductivity type in the semiconductor layer to form inner and outer sinker regions. The inner sinker region is configured to establish a common collector region of first and second bipolar transistor devices. A second well implantation procedure implants dopant of the first conductivity type in the semiconductor layer to form respective base regions of the first and second bipolar transistor devices. Conduction of the first bipolar transistor device is triggered by breakdown between the inner sinker region and the base region of the first bipolar transistor device. Conduction of the second bipolar transistor device is triggered by breakdown between the outer sinker region and the base region of the second bipolar transistor device.

Power amplifier having staggered cascode layout for enhanced thermal ruggedness. In some embodiments, a radio-frequency (RF) amplifier such as a power amplifier (PA) can be configured to receive and amplify an RF signal. The PA can include an array of cascoded devices connected electrically parallel between an input node and an output node. Each cascoded device can include a common emitter transistor and a common base transistor arranged in a cascode configuration. The array can be configured such that the common base transistors are positioned in a staggered orientation relative to each other.

An integrated circuit contains a logic MOS transistor and a memory MOS transistor of a same polarity. The logic MOS transistor has a logic channel stop layer. The memory MOS transistor has a memory channel stop layer. An average dopant density of the memory channel stop layer is higher than an average dopant density of the logic channel stop layer. The integrated circuit is formed by forming a global mask which exposes both the logic and memory MOS transistors. A global channel stop dose of dopants is implanted in the logic and memory MOS transistors. A memory mask is formed which exposes the memory MOS transistor and covers the logic MOS transistor. A memory channel stop dose of dopants of the same polarity is implanted into the memory MOS transistors. The memory channel stop dose of dopants are blocked from the logic MOS transistors.