A semiconductor device includes: first and second semiconductor elements, each of which has first and second electrodes; a first lead mounting the first semiconductor element; a second lead mounting the second semiconductor element; a sealing resin covering the first and second semiconductor elements; a third lead disposed apart from the first and second leads in a y direction, exposed from the sealing resin, and electrically connected to the first electrode of the first semiconductor element; a fifth lead disposed apart from the first and second leads on the opposite side to the third lead, exposed from the sealing resin, and electrically connected to the second electrode of the first semiconductor element; and a sixth lead disposed apart from the first and second leads on the same side as the fifth lead, exposed from the sealing resin, and electrically connected to the second electrode of the second semiconductor element.

Aspects of the disclosure provide a bipolar transistor structure with a sub-collector on a substrate, a first collector region on a first portion of the sub-collector, a trench isolation (TI) on a second portion of the sub-collector and adjacent the first collector region, and a second collector region on a third portion of the sub-collector and adjacent the TI. A base on first collector region and a portion of the TI. An emitter is on a first portion of the base above the first collector region. The base includes a second portion horizontally displaced from the emitter in a first horizontal direction, and horizontally displaced from the second collector region in a second horizontal direction orthogonal to the first horizontal direction.

A substrate current suppression circuit includes: a fixed voltage line that supplies a fixed voltage to the collectors of the third and fourth transistors. The fixed voltage is a voltage higher than the base voltage of the third and fourth transistors when the first polarity is p type, and is a voltage lower than the base voltage when the first polarity is n type.

A bipolar transistor includes a collector region having a first doped portion located in a substrate and a second doped portion covering and in contact with an area of the first doped portion. The collector region has a doping profile having a peak in the first portion and a decrease from this peak up to in the second portion.

The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich isolation region and methods of manufacture. The structure includes: a first heterojunction bipolar transistor; a second heterojunction bipolar transistor; and a trap rich isolation region embedded within a substrate underneath both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor.

The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich isolation region and methods of manufacture. The structure includes: a first heterojunction bipolar transistor; a second heterojunction bipolar transistor; and a trap rich isolation region embedded within a substrate underneath both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor.

A compound semiconductor device comprises a heterojunction bipolar transistor including a plurality of unit transistors, a capacitor electrically connected between a RF input wire and a base wire for each unit transistor of the unit transistors, and a bump electrically connected to emitters of the unit transistors. The unit transistors are arranged in a first direction. The bump is disposed above the emitters of the unit transistors while extending in the first direction. The transistors include first and second unit transistors, the respective emitters of the first and second unit transistors being disposed on first and second sides, respectively, of a second direction, perpendicular to the first direction, with respect to a center line of the bump extending in the first direction. The capacitor is not covered by the bump, and respective lengths of the respective base wires connected respectively to the first and second unit transistors are different.

A self-powered electronic system comprises a first chip of single-crystalline semiconductor embedded in a second chip of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container bordered by ridges. The flat side of the slab includes a heavily n-doped region forming a pn-junction with the p-type bulk. A metal-filled deep silicon via through the p-type ridge connects the n-region with the terminal on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.

A self-powered electronic system comprises a first chip of single-crystalline semiconductor embedded in a second chip of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container bordered by ridges. The flat side of the slab includes a heavily n-doped region forming a pn-junction with the p-type bulk. A metal-filled deep silicon via through the p-type ridge connects the n-region with the terminal on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.

A multi-transistor configuration including a first transistor having a first terminal that is configured to control the flow of current between, a second terminal of the first transistor and a third terminal of the first transistor; a second transistor, that is a bipolar junction transistor comprising a base terminal, an emitter terminal, and a collector terminal, wherein the third terminal of the first transistor and the collector terminal of the second transistor are electrically connected; and a first voltage source having a first terminal at a first voltage and a second terminal at a second voltage.