IC apparatus, and manufacturing methods therefor, that include a power transistor and a thermoelectric device. The power transistor is constructed in a plurality of layers formed over a semiconductor substrate. The thermoelectric device is formed in one or more of the plurality of layers and is sensitive to temperature differences within the IC apparatus resulting from operation of the power transistor.

A III-nitride semiconductor based heterojunction power device including: a first heterojunction transistor formed on a substrate, and a second heterojunction transistor formed on the substrate. One of the first heterojunction transistor and the second heterojunction transistor is an enhancement mode field effect transistor and the other one of the first heterojunction transistor and the second heterojunction transistor is a depletion mode field effect transistor. The enhancement mode transistor acts as a main power switch, and the depletion mode transistor acts as a start-up component.

In an embodiment, a switching circuit is provided that includes a Group III nitride-based semiconductor body including a first monolithically integrated Group III nitride-based transistor device and a second monolithically integrated Group III nitride based transistor device that are coupled to form a half-bridge circuit and are arranged on a common foreign substrate having a common doping level. The switching circuit is configured to operate the half-bridge circuit at a voltage of at least 300V.

A GaN epitaxial substrate comprises a growth substrate and a multilayer structure grown on the growth substrate in the Ga-polar direction. The multilayer structure comprises: a buffer layer, an n-type conductive layer formed on the buffer layer, a first GaN layer formed on the n-type conductive layer, an electron supply layer formed on the first GaN layer, and a second GaN layer formed on the electron supply layer.

In one embodiment, an integrated circuit includes a silicon substrate, a gallium nitride (GaN) layer above the silicon substrate, a bonding layer above the GaN layer, and a silicon layer above the bonding layer. Further, the integrated circuit includes a first transistor on the GaN layer and a second transistor on the silicon layer.

An electronic device includes an one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride back barrier layer over a buffer structure, a gallium nitride layer over the back barrier layer, a hetero-epitaxy structure over the gallium nitride layer, first and second transistors over the hetero-epitaxy structure, and a hole injector having a doped gallium nitride structure over the hetero-epitaxy structure and a conductive structure partially over the doped gallium nitride structure to inject holes to form a hole layer proximate an interface of the back barrier layer and the buffer structure to mitigate vertical electric field back gating effects for the first transistor.

The present invention provides an epitaxial structure of Ga-face group III nitride, its active device, and the method for fabricating the same. The epitaxial structure of Ga-face AlGaN/GaN comprises a substrate, an i-GaN (C-doped) layer on the substrate, an i-Al(y)GaN buffer layer on the i-GaN (C-doped) layer, an i-GaN channel layer on the i-Al(y)GaN buffer layer, and an i-Al(x)GaN layer on the i-GaN channel layer, where x=0.1˜0.3 and y=0.05˜0.75. By using the p-GaN inverted trapezoidal gate or anode structure in device design, the 2DEG in the epitaxial structure of Ga-face group III nitride below the p-GaN inverted trapezoidal structure will be depleted, and thus fabricating p-GaN gate enhancement-mode (E-mode) AlGaN/GaN high electron mobility transistors (HEMTs), p-GaN anode AlGaN/GaN Schottky barrier diodes (SBDs), or hybrid devices.

Apparatus and circuits with dual threshold voltage transistors and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a first layer comprising a first III-V semiconductor material formed over the substrate; a first transistor formed over the first layer, and a second transistor formed over the first layer. The first transistor comprises a first gate structure comprising a first material, a first source region and a first drain region. The second transistor comprises a second gate structure comprising a second material, a second source region and a second drain region. The first material is different from the second material.

A semiconductor device includes a layer stack with first semiconductor layers and second semiconductor layers of opposite doping types arranged alternatingly. A first semiconductor region of a first semiconductor device adjoins the first semiconductor layers, and has a first end arranged in a first region of the first semiconductor device and extends from the first end into a second region of the first semiconductor device. Second semiconductor regions of the first semiconductor device adjoin at least one of the second semiconductor layers. A third semiconductor region of the first semiconductor device adjoins the first semiconductor layers. The first semiconductor region extends from the first region into the second region and is spaced apart from the third semiconductor region. The second semiconductor regions are arranged between, and spaced apart from, the third and first semiconductor regions. An average doping concentration along a shortest path between the first and third semiconductor regions in at least one of the first or second semiconductor layers in the first region differs from an average doping concentration along a shortest path between the first and third semiconductor regions of the same layer in the second region.

A field-effect transistor includes: a nitride semiconductor layer that includes a heterojunction; a source electrode and a drain electrode that are disposed on the nitride semiconductor layer at an interval; a first gate electrode that is located between the source electrode and the drain electrode and performs a normally-on operation; and a second gate electrode that is located between the first gate electrode and the source electrode and performs a normally-off operation. The first gate electrode is disposed to surround the drain electrode in plan view. The second gate electrode is disposed to surround the source electrode in plan view.