A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.

A resistance circuit is configured such that a P-type resistance section and an N-type resistance section are electrically connected in series, the P-type resistance section is configured with P-type diffusion layer resistance elements that are disposed to form a right angle with respect to each other and that are electrically connected in series, and the N-type resistance section is configured with N-type diffusion layer resistance elements that are disposed to form the right angle with respect to each other and that are electrically connected in series. Furthermore, the P-type diffusion layer resistance element is disposed along a <100> orientation direction of a semiconductor substrate, and the N-type diffusion layer resistance element is disposed along a <110> orientation direction of the semiconductor substrate. It is thereby possible to provide the resistance circuit, an oscillation circuit, and an in-vehicle sensor apparatus that reduce stress-induced characteristic fluctuations.

An integrated circuit includes a substrate layer and a resistor bank in a polysilicon layer disposed on the substrate layer. The resistor bank includes a plurality of resistor elements having a body portion extending in a longitudinal direction. A metal line is disposed in a metal layer above the polysilicon layer to extend transverse to the longitudinal direction and across the body portion of a group of the plurality of resistor elements, thereby forming a first region of the resistor bank and a second region of the resistor bank. The first region is separated from the second region by the metal line. A resistor device having a predetermined resistance includes a subset of the resistor elements in the group electrically coupled together in the second region. The resistor device also includes first and second terminals located in the same first or second region of the resistor bank.

A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The features extend horizontally though a primary portion of the stack with at least some of the features extending farther in the horizontal direction in an end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the openings. Other aspects and implementations are disclosed.

Embodiments relate to a semiconductor structure, including: an active layer including a channel region; a first dielectric layer covering a top surface of the channel region; a gate layer covering a top surface of the first dielectric layer, where the active layer, the first dielectric layer and the gate layer constitute a first capacitor, and the first capacitor is coupled between a first potential and a second potential; two groups of first conductive layers, where the first conductive layers among the two groups of first conductive layers are electrically connected to each other; two groups of second conductive layers, where each of the second conductive layers clads a side surface and a bottom surface of the first conductive layer, one group of the second conductive layers is electrically connected to a third potential, and the other group of the second conductive layers is electrically connected to a fourth potential.

In some embodiments, the present disclosure relates to a memory circuit having a first resistive random access memory (RRAM) element and a second RRAM element arranged within a dielectric structure over a substrate. The first RRAM element has a first conjunct electrode separated from a first disjunct electrode by a first data storage layer. The second RRAM element has a second conjunct electrode separated from a second disjunct electrode by a second data storage layer. A control device is disposed within the substrate and has first terminal coupled to the first conjunct electrode and the second conjunct electrode and a second terminal coupled to a word-line.

A semiconductor device includes; a bottom electrode on a substrate, a supporting pattern between the bottom electrode and an adjacent bottom electrode, a top electrode covering the bottom electrode and the supporting pattern, and a dielectric layer between the bottom electrode and the top electrode and between the supporting pattern and the top electrode. The bottom electrode may include a first portion including a seam and a second portion on the first portion, a top end of the second portion may be disposed at a height lower than an upper surface of the supporting pattern, and a portion of a bottom end of the second portion may be exposed to the seam.

A storage array and a storage chip and method for storing a logic relationship between objects. The storage array comprises first leading-out wires and second leading-out wires, and a storage unit is connected between each first leading-out wire and each second leading-out wire having different serial numbers. A controllable switch is connected between each first leading-out wire and each second leading-out wire having a same serial number. The storage chip comprises an interface module. A control module is used for producing a control signal. A driving module is used for producing write current, erase current or read current. A first decoder and a second decoder are used for gating the first leading-out wires and the second leading-out wires. A storage array is used for storing a logic relationship value. The storage method comprises write and read operations.

A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the horizontally elongated openings. Other aspects and implementations are disclosed.

A fingerprint sensing chip and a terminal device are provided. The fingerprint sensing chip includes a first signal, a second signal and a driving signal. The second signal is generated based on the first signal, and the driving signal is generated by performing a ground raise process on the second signal. The driving signal is used to provide a driving voltage for fingerprint sensing.