A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; first metal layers interconnecting at least said first transistors; a second metal layer overlaying said first metal layers; and a second level comprising a second single crystal layer, said second level comprising second transistors, wherein said second level overlays said first level, wherein at least one of said second transistors comprises a gate all around structure, wherein said second level is directly bonded to said first level, and wherein said bonded comprises direct oxide to oxide bonds.

A magnetoresistance effect element has an underlayer, a first ferromagnetic metal layer, a second ferromagnetic metal layer, and a tunnel barrier layer that is sandwiched between the first and second ferromagnetic metal layers. The tunnel barrier layer has a spinel structure and includes at least one lattice-matched portion, and at least one lattice-mismatched portion. The underlayer is made of a nitride layer; a layer having a (001)-oriented tetragonal or cubic structure; or a layer having a stacked structure with a combination of a nitride layer having a (001)-oriented NaCl structure and a layer having a (001)-oriented tetragonal or cubic structure.

A magnetoresistance effect element has an underlayer, a first ferromagnetic metal layer, a second ferromagnetic metal layer, and a tunnel barrier layer that is sandwiched between the first and second ferromagnetic metal layers. The tunnel barrier layer has a spinel structure and includes at least one lattice-matched portion, and at least one lattice-mismatched portion. The underlayer is made of a nitride layer; a layer having a (001)-oriented tetragonal or cubic structure; or a layer having a stacked structure with a combination of a nitride layer having a (001)-oriented NaCl structure and a layer having a (001)-oriented tetragonal or cubic structure.

A tunnel magnetoresistance effect (TMR) device includes an exchange coupling film having a first ferromagnetic layer, which is at least a portion of a fixed magnetic layer, and an antiferromagnetic layer laminated on the first ferromagnetic layer. The ferromagnetic layer includes an X(Cr—Mn) layer containing one or two or more elements X selected from the group consisting of the platinum group elements and Ni, and also containing Mn and Cr. The X(Cr—Mn) layer has a first region relatively near the first ferromagnetic layer, and a second region relatively far away from the first ferromagnetic layer, and the content of Mn in the first region is higher than that in the second region.

This spin current magnetization rotational type magnetoresistive element includes a magnetoresistive effect element having a first ferromagnetic metal layer having a fixed magnetization orientation, a second ferromagnetic metal layer having a variable magnetization orientation, and a non-magnetic layer sandwiched between the first ferromagnetic metal layer and the second ferromagnetic metal layer, and spin-orbit torque wiring which extends in a direction that intersects the stacking direction of the magnetoresistive effect element, and is connected to the second ferromagnetic metal layer, wherein the electric current that flows through the magnetoresistive effect element and the electric current that flows through the spin-orbit torque wiring merge or are distributed in the portion where the magnetoresistive effect element and the spin-orbit torque wiring are connected.

This spin current magnetization rotational type magnetoresistive element includes a magnetoresistive effect element having a first ferromagnetic metal layer having a fixed magnetization orientation, a second ferromagnetic metal layer having a variable magnetization orientation, and a non-magnetic layer sandwiched between the first ferromagnetic metal layer and the second ferromagnetic metal layer, and spin-orbit torque wiring which extends in a direction that intersects the stacking direction of the magnetoresistive effect element, and is connected to the second ferromagnetic metal layer, wherein the electric current that flows through the magnetoresistive effect element and the electric current that flows through the spin-orbit torque wiring merge or are distributed in the portion where the magnetoresistive effect element and the spin-orbit torque wiring are connected.

According to one embodiment, a memory system classifies a plurality of nonvolatile memory dies connected to a plurality of channels, into a plurality of die groups such that each of the plurality of nonvolatile memory dies belongs to only one die group. The memory system performs a data write/read operation for one die group of the plurality of die groups in accordance with an I/O command from a host designating one of a plurality of regions including at least one region corresponding to each die group. The memory system manages a group of free blocks in the nonvolatile memory for each of the plurality of die group by using a plurality of free block pools corresponding to the plurality of die groups.

A magnetoresistive memory cell includes an MTJ element including a magnetization free layer and a pure spin injection source. The pure spin injection source includes a BiSb layer coupled to the magnetization free layer. By flowing an in-plane current through the BiSb layer, this arrangement is capable of providing magnetization reversal of the magnetization free layer.

An IC is provided. The IC includes a plurality of a plurality of P-type fin field-effect transistors (FinFETs). The P-type FinFETs includes at least one first P-type FinFET and at least one second P-type FinFET. Source/drain regions of the first P-type FinFET have a first depth, and source/drain regions of the second P-type FinFET have a second depth that is different from the first depth. A first semiconductor fin of the first P-type FinFET includes a first portion and a second portion that are formed by different materials, and the second portion of the first semiconductor fin has a third depth that is greater than the first depth.

A semiconductor package includes: a first semiconductor chip stack including a plurality of first semiconductor chips which are stacked in a vertical direction; a bridge die stack disposed to be spaced apart from the first semiconductor chip stack in a horizontal direction and including a plurality of bridge dies which are stacked in the vertical direction, wherein the bridge dies include through electrodes, respectively, and the through electrodes aligned in the vertical direction are connected to each other through a connection electrode between the bridge dies; a redistribution layer disposed over the first semiconductor chip stack and the bridge die stack; a second semiconductor chip disposed over the redistribution layer and configured to receive a voltage through the through electrodes aligned in the vertical direction, the connection electrode, and the redistribution layer; and a voltage regulator configured to adjust the voltage.