An image sensor configured to decrease crosstalk by reducing a color filter thickness, and an electronic apparatus including the image sensor are provided. The image sensor includes: a sensor substrate including a plurality of first pixels and a plurality of second pixels; and a color filter array including a plurality of first color filters respectively corresponding to the plurality of first pixels and a plurality of second color filters respectively corresponding to the plurality of second pixels, wherein each of the plurality of first color filters and the plurality of second color filters includes: an absorption-type filter layer including a polymer-based pigment; and a resonator including a first reflective film provided on a lower surface of the absorption-type filter layer and a second reflective film provided on an upper surface of the absorption-type filter layer, to allow light to resonate in the absorption-type filter layer.

An imaging pixel design is provide with a photo-sensor block structure that facilitates dynamic control of well capacity in the photodiode region (i.e., a “well capacity adjustment (WCA) gate photo-sensor block”). The photodiode region includes a doped well in which photocharge is accumulated responsive to exposure to incident illumination. The capacity of the well corresponds to a well potential. WCA structures (e.g., deep trench regions) form walls at least partially surrounding and capacitively coupling with the doped well, such that biasing of the WCA structures changes the well potential and the corresponding well capacity. As such, the WCA structures can be biased during integration to increase the well potential to a high level for large well capacity, and the WCA structures can be differently biased during photocharge transfer to decrease the well potential to a sufficiently low level that avoids lag and/or other conventional concerns.

A pixel includes a photodiode and first and second transistors, the first and second transistors being coupled in series. One of the first and second transistors is a P channel transistor and the other is an N channel transistor. An electronic device may include one or more of the pixels.

The disclosure provides an image sensor integrated chip and a method for forming the same. The image sensor integrated chip includes a substrate, an isolation structure, an image sensing element, a gate structure, a first dielectric layer, and a reflective layer. The substrate includes a pixel region. The isolation structure is disposed in the substrate and is configured at opposite sides of the pixel region. The image sensing element is disposed in the pixel region of the substrate. The gate structure is disposed on the pixel region of the substrate. The first dielectric layer is disposed above the pixel region of the substrate and covers sidewalls and a portion of a top surface of the gate structure. The reflective layer is disposed on the first dielectric layer. The reflective layer overlaps with the image sensing element and the portion of the top surface of the gate structure in a first direction perpendicular to a surface of the substrate.

An imaging device including pixels including a first pixel and a second pixel, the pixels arranged in rows and columns, the first pixel belonging to a first column, the second pixel belonging to a second column adjacent the first column; a first signal path through which a signal from the first pixel flows; and a second signal path through which a signal from the second pixel flows, a first circuit including first and second lines, a first voltage being applied to the first lines, a second voltage different from the first voltage applied to the second lines. The first signal path is located in a region closer to one of the first lines than any of the second lines in a plan view, and the second signal path is located in a region closer to one of the second lines than any of the first lines in the plan view.

An image sensor includes a pixel division structure, a light sensing element, a color filter array layer and a microlens. The pixel division structure extends through a substrate in a vertical direction, and defines unit pixel regions. The light sensing element is in each unit pixel region. The color filter array layer including color filters is on the substrate. The microlens is on the color filter array layer. The pixel division structure includes a core and a lateral pattern structure on a sidewall thereof. The core includes a first filling pattern including polysilicon doped with impurities at a first concentration and a second filling pattern in a space formed by the first filling pattern. A sidewall of the second filling pattern is covered by the first filling pattern, and the second filling pattern includes polysilicon doped with impurities at a second concentration different from the first concentration.

Photoelectric conversion apparatus including semiconductor layer includes pixel array region and peripheral region. The semiconductor layer has first and second faces. Each pixel includes first semiconductor region of first conductivity type arranged on the first face side and second semiconductor region of second conductivity type arranged on the second face side, and predetermined voltage causing avalanche multiplication operation is supplied between the first semiconductor region and the second semiconductor region. The peripheral region includes third semiconductor region of the first conductivity type arranged on the first face side, fourth semiconductor region of the second conductivity type arranged apart from the third semiconductor region, and fifth semiconductor region of the first conductivity type arranged, close to the third semiconductor region, between the third semiconductor region and the fourth semiconductor region.

A photoelectric conversion device includes a connecting portion that electrically connects a contact plug of anode wiring and the second semiconductor region of the isolation portion. The connecting portion includes a third semiconductor region of the second conducting type that is connected to the contact plug of the anode wiring, and a fourth semiconductor region of the second conducting type that is disposed between the third semiconductor region and the second semiconductor region. The impurity concentration of the third semiconductor region is higher than the impurity concentration of the second semiconductor region and the impurity concentration of the fourth semiconductor region is lower than the impurity concentration of the third semiconductor region. With respect to a direction in which the APDs are arrayed, the width of the isolation portion is smaller than the width of the connecting portion.

A backside-illuminated image sensor includes arrayed photodiodes separated by isolation structures, and interlayer dielectric between first layer of metal interconnect and substrate. The image sensor has barrier metal walls in the interlayer dielectric between isolation structures and first layer interconnect, the barrier metal walls aligned with the isolation structures and disposed between the isolation structures and first layer interconnect. The barrier metal wall deflects light passing through photodiodes of the sensor that would otherwise be reflected by interconnect into different photodiodes. The sensor is formed by providing a partially fabricated semiconductor substrate with photodiodes and source-drain regions formed; forming gate electrodes on a frontside surface of the semiconductor substrate, depositing an etch-stop layer over the gate electrodes; depositing interlayer dielectric on the etch-stop layer; forming trenches extending to the etch-stop layer through the interlayer dielectric, the trenches being between photodiodes; and filling trenches with metal to form barrier metal walls.

Pixels, such as for image sensors and electronic devices, include a photodiode formed in a semiconductor substrate, a floating diffusion, and a transfer structure selectively coupling the photodiode to the floating diffusion. The transfer structure includes a transfer gate formed on the semiconductor substrate, and a vertical channel structure including spaced apart first doped regions formed in the semiconductor substrate between the transfer gate and the photodiode. Each spaced apart first doped region is doped at a first dopant concentration with a first-type dopant. The spaced apart first doped regions are formed in a second doped region doped at a second dopant concentration with a second-type dopant of a different conductive type.