A photoelectric conversion apparatus includes a first semiconductor layer having a photoelectric conversion element, a second semiconductor layer including circuitry for processing a signal based on a charge obtained by the photoelectric conversion element, a first wiring structure electrically connected to the first semiconductor layer, a second wiring structure electrically connected to the second semiconductor layer, and a coupling part that couples the first wiring structure to the second wiring structure. In a plan view, the apparatus includes a pixel region having the photoelectric conversion element, and a peripheral region located between the pixel region and an outer edge of the photoelectric conversion apparatus. The first wiring structure includes, in the peripheral region, a first conductive part having a mesh-shaped part. The first conductive part is connected to a pad facing outside the photoelectric conversion apparatus.

A photoelectric conversion apparatus includes a semiconductor layer having an avalanche photodiode, and a wiring structure electrically connected to the semiconductor layer. In a plan view, the photoelectric conversion apparatus comprises a pixel region including the avalanche photodiode, and a peripheral region located between the pixel region and an outer edge of the photoelectric conversion apparatus. A third wiring layer is located between a first wiring layer and a second wiring layer. The first wiring layer includes, in the peripheral region, a first conductive part for transmitting an anode potential of the avalanche photodiode. The second wiring layer includes, in the peripheral region, a second conductive part for transmitting a second potential different from the anode potential. The first conductive part and the second conductive part overlap in the plan view.

A photoelectric conversion device includes a pixel, the pixel including an avalanche photodiode, and a signal processing circuit including a counter configured to generate a count value based on a photon incident on the avalanche photodiode during a count period, the signal processing circuit being configured to output the count value for each count period repeatedly. The pixel transitions from a first state to a second state in which a length of the count period is shorter than that in the first state in accordance with a result of determination based on the count value and a predetermined threshold value.

An image sensor including: a substrate which has a first surface and a second surface opposite to the first surface and pixels arranged in a two-dimensional array, wherein each of the pixels includes a photodiode; a multi-wiring layer arranged on the first surface of the substrate; a color filter layer arranged on the second surface of the substrate and including color filters that respectively correspond to the pixels; and a lens layer arranged on the color filter layer and including a double-sided spherical lens, wherein the double-sided spherical lens includes at least two material layers having different refractive indexes.

A semiconductor image sensor includes a plurality of pixels. Each pixel of the sensor includes a semiconductor substrate having opposite front and back sides and laterally delimited by a first insulating wall including a first conductive core insulated from the substrate, electron-hole pairs being capable of forming in the substrate due to a back-side illumination. A circuit is configured to maintain, during a first phase in a first operating mode, the first conductive core at a first potential and to maintain, during at least a portion of the first phase in a second operating mode, the first conductive core at a second potential different from the first potential.

The present invention provides a semiconductor structure for forming a CMOS image sensor. The semiconductor structure includes at least a photodiode formed in the substrate for collecting photoelectrons, and the photodiode has a pinning layer, a first doped region and a second doped region in order from top to bottom in a height direction of the substrate. The semiconductor structure further includes a third doped region located in the substrate corresponding to a laterally extending region of the second doped region. The first doped region has an ion doping concentration greater than the ion doping concentration of the second doped region, the ion doping concentration of the second doped region is greater than the ion doping concentration of the third doped region, and the third doped region is in contact with the second doped region after diffusion. The present invention also provides a method of manufacturing the above-described semiconductor structure.

A detection device includes a sensor area in which a plurality of detection elements each comprising a photoelectric conversion element are arranged in a detection region, a drive circuit configured to supply a plurality of drive signals to the detection elements, and a detection circuit configured to process a detection signal output from each of the detection elements.

An image capturing apparatus includes a plurality of photoelectric conversion elements, a first selection unit, and a second selection unit. Each of the photoelectric conversion elements includes an avalanche diode and a counter. The photoelectric conversion elements have a first photoelectric conversion element and a second photoelectric conversion element. The first selection unit controls the first photoelectric conversion element. The second selection unit controls the second photoelectric conversion element. The first and second selection units are controlled by a first control line and a second control line. In a first mode, the second selection unit controls the second photoelectric conversion element to be brought into a state where no signal is read from the second photoelectric conversion element. In a second mode, the second selection unit controls the second photoelectric conversion element to be brought into a state where a signal is read from the second photoelectric conversion element.

An image sensor includes a first photodiode group, a second photodiode group, a first transfer transistor group, a second transfer transistor group, a floating diffusion region of a substrate in which electric charges generated in the first photodiode group are stored, and a power supply node for applying a power supply voltage to the second photodiode group. A barrier voltage is applied to at least one transfer transistor of the second transfer transistor group. The power supply voltage allows electric charges, generated in the second photodiode group, to migrate to the power supply node, and the barrier voltage forms a potential barrier between the second photodiode group and the floating diffusion region.

A method for forming a pixel includes forming, in a semiconductor substrate, a wide trench having an upper depth with respect to a planar top surface of the semiconductor substrate. The method also includes ion-implanting a floating-diffusion region between the planar top surface and a junction depth in the semiconductor substrate. In a cross-sectional plane perpendicular to the planar top surface, the floating-diffusion region has (i) an upper width between the planar top surface and the upper depth, and (ii) between the upper depth and the junction depth, a lower width that exceeds the upper width. Part of the floating-diffusion region is beneath the wide trench and between the upper depth and the junction depth.