A photodiode pixel structure for imaging short wave infrared (SWIR) and visible light built in a planar structure and may be used for one dimensional and two dimensional photodiode arrays. The photodiode arrays may be hybridized to a read out integrated circuit (ROIC), for example, a silicon complementary metal-oxide-semiconductor (CMOS) circuit. The photodiode in each pixel is buried under the surface and does not directly contact the ROIC amplification circuit. Disconnecting the photodiode from the ROIC amplification circuit enables low dark current as well as double correlated sampling in the pixel.

Germanium-based sensors are disclosed herein. An exemplary germanium-based sensor includes a germanium photodiode and a junction field effect transistor (JFET) formed from a germanium layer disposed on and/or in a silicon substrate. A doped silicon layer, which can be formed by in-situ doping epitaxially grown silicon, is disposed between the germanium layer and the silicon substrate. In embodiments where the germanium layer is on the silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. The JFET has a doped polysilicon gate, and in some embodiments, a gate diffusion region is disposed in the germanium layer under the doped polysilicon gate. In some embodiments, a pinned photodiode passivation layer is disposed in the germanium layer. In some embodiments, a pair of doped regions in the germanium layer is configured as an e-lens of the germanium-based sensor.

Germanium-based sensors are disclosed herein. An exemplary germanium-based sensor includes a germanium photodiode and a junction field effect transistor (JFET) formed from a germanium layer disposed on and/or in a silicon substrate. A doped silicon layer, which can be formed by in-situ doping epitaxially grown silicon, is disposed between the germanium layer and the silicon substrate. In embodiments where the germanium layer is on the silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. The JFET has a doped polysilicon gate, and in some embodiments, a gate diffusion region is disposed in the germanium layer under the doped polysilicon gate. In some embodiments, a pinned photodiode passivation layer is disposed in the germanium layer. In some embodiments, a pair of doped regions in the germanium layer is configured as an e-lens of the germanium-based sensor.

A photodiode pixel structure for imaging short wave infrared (SWIR) and visible light built in a planar structure and may be used for one dimensional and two dimensional photodiode arrays. The photodiode arrays may be hybridized to a read out integrated circuit (ROIC), for example, a silicon complementary metal-oxide-semiconductor (CMOS) circuit. The photodiode in each pixel is buried under the surface and does not directly contact the ROIC amplification circuit. Charge is transferred form the detector using a junction field effect transistor (JFET) in each pixel. Disconnecting the photodiode from the ROIC amplification circuit enables low dark current as well as double correlated sampling in the pixel.

A method of fabricating asymmetric vertical field effect transistors (VFETs) includes forming mandrels above a substrate comprising a first semiconductor material. A first set of spacers is formed adjacent to each side of the mandrels, and trenches are formed in portions of the substrate that are not below one of the mandrels or one of the first set of spacers. The method also includes filling the trenches with a second semiconductor material that is different from the first semiconductor material and forming a second set of spacers adjacent to each respective one of the first set of spacers. The second set of spacers is above the second semiconductor material. A plurality of fins is formed such that each one of the plurality of fins includes a portion of the substrate and a portion of the second semiconductor material. Gates are formed between each adjacent pair of fins.

Some embodiments provide an image sensor pixel comprising a junction field effect transistor (JFET) and a floating diffusion configured to act as the gate of the JFET. An image sensor may comprise a plurality of pixels, at least one pixel comprising a floating diffusion region formed in a semiconductor substrate, a transfer gate configured to selectively cause transfer of photocharge stored in the pixel to the floating diffusion, and a JFET having (i) a source and a drain coupled by a channel region, and (ii) a gate comprising the floating diffusion region.

At least one solid-state image sensor includes a first photoelectric conversion unit configured to convert light into an electric charge, a first field effect transistor including a gate to which the electric charge converted by the first photoelectric conversion unit is input, and a bipolar transistor including a base and an emitter, the base being connected to a source of the first field effect transistor, and the emitter being configured to output a signal.

An imaging device according to an embodiment of the present disclosure includes: a first substrate including a sensor pixel that performs photoelectric conversion; a second substrate including a pixel circuit that outputs a pixel signal on a basis of electric charges outputted from the sensor pixel; and a third substrate including a processing circuit that performs signal processing on the pixel signal. The first substrate, the second substrate, and the third substrate are stacked in this order, and a concentration of electrically-conductive type impurities in a region on side of the first substrate is higher than a concentration of electrically-conductive type impurities in a region on side of the third substrate, in at least one or more semiconductor layers in which a field-effect transistor of the pixel circuit is provided.