Disclosed herein is a solid state imaging device including a support substrate; an imaging semiconductor chip having a pixel array disposed on the support substrate; and an image processing semiconductor chip disposed on the support substrate, wherein the imaging semiconductor chip and the image processing semiconductor chip are connected by through-vias, and interconnects formed on the support substrate.

A method for forming a through-substrate via structure includes providing a substrate and providing a conductive via structure adjacent to a first surface of the substrate. The method includes providing a recessed region on an opposite surface of the substrate towards the conductive via structure. The method includes providing an insulator in the recessed region and providing a conductive region extending along a first sidewall surface of the recessed region in the cross-sectional view. In some examples, the first conductive region is provided to be coupled to the conductive via structure and to be further along at least a portion of the opposite surface of the substrate outside of the recessed region. The method includes providing a protective structure within the recessed region over a first portion of the first conductive region but not over a second portion of the first conductive region that is outside of the recessed region. The method includes attaching a conductive bump to the second portion of the first conductive region.

The height of a solid-state imaging element is further reduced as compared to the related art. A solid-state imaging element that is a wafer-level chip size package, including: an optical sensor chip; a protective layer that is stacked on a light receiving surface of the optical sensor chip; and a rewiring layer that is stacked on a surface opposite to the light receiving surface of the optical sensor chip, in which a connection terminal of the rewiring layer is a copper flat pad without a solder ball, an alloy layer of tin and copper is not formed on a front surface of the flat pad, and a thermal expansion coefficient of the protective layer is substantially balanced with a thermal expansion coefficient of the rewiring layer.

The present invention relates to an embedded printed circuit board including: an insulation substrate including a cavity; a sensor device disposed on the cavity; an insulating layer disposed on the insulation substrate, having an opening part exposing the sensor device; and a pad part disposed on the lower surface of the opening part exposing the sensor device.

A semiconductor apparatus configured to decrease occurrence of exfoliation between a conductor layer and an insulator layer is provided. A first region containing silicon and copper is disposed between a first conductor portion and a first insulator portion. A second region containing silicon and copper is disposed between a second conductor portion and a second insulator portion. The first region has a maximum nitrogen concentration higher than that of the second region.

An image sensor structure including an image stack disposed over a device stack. The image stack includes a plurality of light detectors. A first optical filter stack is disposed over the image stack. The first optical filter stack includes a light guide layer. Light pipe cavities are disposed in the light guide layer. Each light pipe cavity is associated with a light detector. Each light pipe cavity has an aspect ratio that is greater than about 2.5 to about 1. A nanowell layer is disposed over the first optical filter stack. Nanowells are disposed in the nanowell layer. Each nanowell is associated with a light detector.

The present disclosure relates to a semiconductor element, a manufacturing method of a semiconductor element, and an electronic apparatus, which enable suppression of crack occurrences and leaks. The present technology has a laminated structure including an insulating film having a CTE value between those of metal and Si and disposed under a metal wiring, and P—SiO (1 μm) having good coverage and disposed as a via inner insulating film in a TSV side wall portion. As the insulating film having a CTE that is in the middle between those of metal and Si, for example, SiOC is used with a thickness of 0.1 μm and 2 μm respectively in the via inner insulating film and a field top insulating film continuous to the via inner insulating film. The present disclosure can be applied to, for example, a solid-state imaging element used in an imaging device.

A semiconductor substrate includes a matrix of photosites. Each photosite is delimited by an isolation trench including polycrystalline silicon. A peripheral zone extends directly around the matrix of photosites. The peripheral zone includes dummy photosites delimited by isolation trenches including polycrystalline silicon. A density of polycrystalline silicon in the peripheral zone is between a density of polycrystalline silicon at an edge of the matrix of photosites and a density of polycrystalline silicon around the peripheral zone.

A pixel sensor may include a deep trench isolation (DTI) structure that extends the full height of a substrate in which a photodiode of the pixel sensor is included. Incident light entering the pixel sensor at a non-orthogonal angle is absorbed or reflected by the DTI structure along the full height of the substrate. In this way, the DTI structure may reduce, minimize, and/or prevent the incident light from traveling through the pixel sensor and into an adjacent pixel sensor along the full height of the substrate. This may increase the spatial resolution of an image sensor in which the DTI structure is included, may increase the overall sensitivity of the image sensor, may reduce and/or prevent color mixing between pixel sensors of the image sensor, and/or may decrease image noise after color correction.

Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes and image sensor element disposed within a substrate. The substrate comprises a first material. The image sensor element includes an active layer comprising a second material different from the first material. A buffer layer is disposed between the active layer and the substrate. The buffer layer extends along outer sidewalls and a bottom surface of the active layer. A capping structure overlies the active layer. Outer sidewalls of the active layer are spaced laterally between outer sidewalls of the capping structure such that the capping structure continuously extends over outer edges of the active layer.