A semiconductor device includes conductive pillars on a semiconductor substrate, a first support pattern that contacts first portions of lateral surfaces of the conductive pillars and connects the conductive pillars to each other, the first support pattern including first support holes that expose second portions of the lateral surfaces of the conductive pillars, a capping conductive pattern that contacts the second portions of the lateral surfaces of the conductive pillars and exposes the first support pattern, the second portions of the lateral surfaces of the conductive pillars being in no contact with the first support pattern, and a dielectric layer that covers the first support pattern and the capping conductive pattern, the dielectric layer being spaced apart from the conductive pillars.

Multi-plate MIM capacitors include a staircase structure, with steps including a high-k capacitor dielectric and one or more electrode plates. Contacts pass through insulator fill material and land on the electrode plate of a respective step. A recess passes through the staircase structure. In some examples, the recess is filled with insulator material, and steps of the staircase structure have a bilayer structure (e.g., lower layer of capacitor dielectric and upper layer of capacitor electrode plate). In other examples, the recess is filled with conductive material. In such cases, steps of the staircase structure have a multilayer structure that includes an upper portion and a lower portion. The lower portion includes insulator material and the upper portion includes a layer of capacitor dielectric between first and second capacitor electrode plates, with the second capacitor electrode plates being continuous with, or otherwise in contact with, the conductive material in the recess.

A substrate for semiconductor module includes a plurality of insulating layers sequentially stacked on one another, N signal lines transmitting N signals respectively, the N signal lines having N vias that at least partially penetrate through the plurality of insulating layers and are arranged in an N-sided polygon shape in a plan view, and a capacitor element configured to provide capacitive coupling between the N signal lines, the capacitor element having a first coupling element that provides capacitive coupling between first and second vias adjacent to each other among the N vias and a second coupling element that provides capacitive coupling between third and fourth vias that are not adjacent to each other among the N vias.

Some embodiments include a capacitive unit having two or more capacitive tiers. Each of the capacitive tiers has first electrode material arranged in a configuration having laterally-extending first segments and longitudinally-extending second segments. The first and second segments join at intersection-regions. The first electrode material of the first and second segments is configured as tubes. The capacitive tiers are together configured as a stack having a first side. The first electrode material caps the tubes along the first side. Capacitor dielectric material lines the tubes. Second electrode material extends into the lined tubes. Columns of the second electrode material extend vertically through the capacitive tiers and are joined with the second electrode material within the lined tubes. A conductive plate extends vertically along the first side of the stack and is directly against the first electrode material. Some embodiments include methods of forming integrated assemblies.

There is provided a semiconductor device capable of improving performance and reliability of a device, by adjusting the arrangement of penetration patterns included in an electrode support for supporting the lower electrode. The semiconductor device includes a plurality of lower electrodes that are aligned with each other on a substrate along a first direction and a second direction different from the first direction, and a first electrode support that supports the lower electrodes, and includes a plurality of first penetration patterns, wherein the first electrode support includes a center region, and an edge region defined along a periphery of the center region, wherein the first penetration patterns include center penetration patterns that are spaced apart by a first interval in the center region, and wherein the first penetration patterns include edge penetration patterns that are spaced apart by a second interval different from the first interval in the edge region.

A method for forming a capacitor array structure includes the following steps: providing a substrate, a capacitor contact being exposed on a surface of the substrate, and the substrate including an array region and a peripheral region; forming a bottom supporting layer covering the substrate and the capacitor contact, the bottom supporting layer having a gap therein; forming a filling layer filling the gap and covering the capacitor contact and the surface of the bottom supporting layer, a thickness of the filling layer located at the peripheral region being larger than that of the filling layer located at the array region; forming supporting layers and sacrificial layers alternately stacked in a direction perpendicular to the substrate; forming a capacitor hole.

A chip tampering detector is disclosed. The chip tampering detector includes a plurality of resistor-capacitor circuits. Each resistor-capacitor circuit includes a capacitor having a planar area that covers a sensitive area of an integrated circuit of the chip. The resistor-capacitor circuits can be probed with an input signal to generate output signals. The output signals can be measured to determine respective time-constants resistor-capacitor circuits. Tampering with a chip can alter the capacitance of a capacitor covering a sensitive area. Accordingly, a significant change of a time-constant of one or more of the resistor-capacitor circuits can be used to detect chip tampering.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first palm portion positioned above a substrate; a second palm portion positioned above the substrate and opposite to the first palm portion; a first finger portion arranged substantially in parallel with a main surface of the substrate, positioned between the first palm portion and the second palm portion, and connecting to the first palm portion; a second finger portion arranged substantially in parallel with the first finger portion, positioned between the first palm portion and the second palm portion, and connecting to the second palm portion; a capacitor insulation layer positioned between the first finger portion and the second finger portion; a first spacer positioned between the first palm portion and second finger portion; and a second spacer positioned between the second palm portion and the first finger portion.

A circuit structure that includes a plurality of stacked conductor layers separated from each other by respective dielectric layers. The conductor layers may include a first set of conductor layers made of a first type conductor material and a second set of conductor layers made of a second type conductor material different from the first. A pair of conductor posts may traverse the stacked conductor layers. A first post may be electrically connected to the first set of conductor layers and electrically insulated from the second set of conductor layers. A second post electrically connected to the second set of conductor layers and electrically insulated from the first set of conductor layers.

In an embodiment, a semiconductor device is provided that includes a lateral transistor device having a source, a drain and a gate, and a monolithically integrated capacitor coupled between the gate and the drain.