The present disclosure provides a method of manufacturing a semiconductor structure, and a semiconductor structure. The method of manufacturing a semiconductor structure includes: providing an initial structure, wherein the initial structure includes a substrate, a laminated structure, and capacitor units, and the laminated structure includes support layers; forming a first mask layer, wherein the first mask layer covers a top surface of the laminated structure; forming a first opening in the first mask layer, wherein the first opening exposes the top surface of the laminated structure, and a projection region of the first opening on the substrate at least partially overlaps with projection regions of the capacitor units on the substrate; forming a shielding structure, wherein the shielding structure is located in the first opening, and the shielding structure covers a sidewall of the first opening.

A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a substrate, a gate structure and a dielectric layer. Herein, the substrate includes discrete semiconductor pillars. The semiconductor pillars are arranged at the top of the substrate and extend in a vertical direction. The substrate further includes a capacitor structure located at the top of the semiconductor pillar. The gate structure is arranged at the middle area of the semiconductor pillar and surrounds the semiconductor pillar. The dielectric layer is located between the gate structure and the semiconductor pillar, and covers the sidewall of the semiconductor pillar.

Embodiments provide a method for fabricating an array structure of a columnar capacitor and a semiconductor structure, relating to the field of semiconductor manufacturing technology. In the method, before a mask layer is removed, a thickness of the mask layer in the peripheral region is first adjusted to be equal to a thickness of the mask layer in the array region, thereby avoiding damage to a top support layer caused by different thicknesses of the mask layer. Moreover, in the method, a thickness of the top support layer is increased by means of a supplementary support layer, to increase support strength of the top support layer, thereby further preventing occurrence of tilt of the columnar capacitor due to insufficient support strength of the top support layer.

Provided are an adapter board and a method for forming the same, a packaging method, and a package structure. One form of a method for forming an adapter board includes: providing a base, including an interconnect region and a capacitor region, the base including a front surface and a rear surface that are opposite each other; etching the front surface of the base, to form a first trench in the base of the interconnect region and form a second trench in the base of the capacitor region; forming a capacitor in the second trench; etching a partial thickness of the base under the first trench, to form a conductive via; forming a via interconnect structure in the conductive via; and thinning the rear surface of the base, to expose the via interconnect structure.

Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.

A memory device includes a substrate, an active layer that is spaced apart from the substrate and laterally oriented, a word line that is laterally oriented in parallel to the active layer along one side of the active layer, an active body that is vertically oriented by penetrating through the active layer, a bit line that is vertically oriented by penetrating through the active layer to be spaced apart from one side of the active body, and a capacitor that is vertically oriented by penetrating through the active layer to be spaced apart from another side of the active body.

A disclosed high-density capacitor includes a top electrode having an electrically conducting material forming a three-dimensional structure. The three-dimensional structure includes a plurality of vertical portions extending in a vertical direction and horizontal portions, that are interleaved within the vertical portions and extend in a first horizontal direction. The high-density capacitor further includes a dielectric layer formed over the top electrode, and a bottom electrode including an electrically conducting material, such that the bottom electrode is separated from the top electrode by the dielectric layer. Further, the bottom electrode envelopes some of the plurality of vertical portions of the top electrode. The disclosed high-density capacitor further includes a plurality of support structures that are aligned with the first horizontal direction such that the horizontal portions of the top electrode are formed under respective support structures. The high-density capacitor has a capacitance that is proportional to the volume of the capacitor.

A semiconductor package structure includes a substrate, a first redistribution layer, a semiconductor die, a silicon capacitor, and a first bump structure. The first redistribution layer is disposed over the substrate. The semiconductor die is disposed over the first redistribution layer. The silicon capacitor is disposed below the first redistribution layer and is electrically coupled to the semiconductor die, wherein the silicon capacitor includes a semiconductor substrate and a plurality of capacitor cells embedded in the semiconductor substrate. The first bump structure is disposed between the silicon capacitor and the substrate.

A semiconductor structure includes an interposer substrate having an upper surface, a lower surface opposite to the upper surface, and a device region. A first redistribution layer is formed on the upper surface of the interposer substrate. A guard ring is formed in the interposer substrate and surrounds the device region. At least a through-silicon via (TSV) is formed in the interposer substrate. An end of the guard ring and an end of the TSV that are near the upper surface of the interposer substrate are flush with each other, and are electrically connected to the first redistribution layer.

The disclosure is directed to an integrated circuit (IC) die stacked with a backer die, including capacitors and thermal vias. The backer die includes a substrate material to contain and electrically insulate one or more capacitors at a back of the IC die. The backer die further includes a thermal material that is more thermally conductive than the substrate material for thermal spreading and increased heat dissipation. In particular, the backer die electrically couples capacitors to the IC die in a stacked configuration while also spreading and dissipating heat from the IC die. Such a configuration reduces an overall footprint of the electronic device, resulting in decreased integrated circuits (IC) packages and module sizes. In other words, instead of placing the capacitors next to the IC die, the capacitors are stacked on top of the IC die, thereby reducing an overall surface area of the package.