Embodiments disclosed herein include a nanosheet transistor for reducing parasitic capacitance. The nanosheet transistor may include a spacer region between a high-k metal gate and an epitaxial layer. The spacer region may include a first nanosheet stack with a first nanosheet and a second nanosheet. The spacer region may include an inner spacer region between the first nanosheet and the second nanosheet, and a side subway region located along an edge of the first nanosheet, the inner spacer region, and the second nanosheet.

An integrated circuit (IC) device includes a fin-type active region extending in a first lateral direction on a device region of a substrate. A gate line extends in a second lateral direction on the fin-type active region. The second lateral direction intersects with the first lateral direction. A source/drain region is adjacent to one side of the gate line on the fin-type active region. A gate contact is on the gate line and connected to the gate line. A source/drain contact is on the source/drain region and includes a first segment facing the gate contact and a second segment integrally connected to the first segment. The second segment extends from the first segment in the second lateral direction. In the first lateral direction, a first distance from the first segment to the gate line is greater than a second distance from the second segment to the gate line.

Described herein are transistors with front-side and back-side routing, and IC devices including such transistors. The transistor includes a channel material having a longitudinal structure and formed in a dielectric material. A source region encloses a first portion of the channel material, a gate electrode encloses a second portion of the channel material, and a drain region encloses a third portion of the channel material. Each of the source region, gate electrode, and drain region have a first face and a second face opposite the first face, the first and second faces co-planar with the faces of the dielectric material. A first contact is coupled to the first face of the source region, and a second contact is coupled to the second face of the source region.

A semiconductor memory device and a method for manufacturing the same. The semiconductor memory device may include a substrate, a first lower wire pattern and a first upper wire pattern stacked on the substrate, and spaced apart from each other; a second lower wire pattern and a second upper wire pattern stacked on the substrate, spaced apart from each other, and spaced apart from the first lower and upper wire patterns; a first gate line surrounding the first lower wire pattern and the first upper wire pattern; a second gate line surrounding the second lower wire pattern and the second upper wire pattern and spaced apart from the first gate line; a first lower source/drain area; a first upper source/drain area; and a first overlapping contact that electrically connects the first lower source/drain area, the first upper source/drain area and the second gate line to each other.

Present disclosure provides a semiconductor structure, including a semiconductor fin having a first portion and a second portion over the first portion, a first conductive region abutting a first lateral surface of the first portion and a first lateral surface of the second portion, a metal gate having a bottom portion and an upper portion, the bottom portion being between the first portion and the second portion of the semiconductor fin, and the upper portion being over the second portion of the semiconductor fin, and a first spacer between the bottom portion of the metal gate and the first conductive region. A method for manufacturing the semiconductor structure described herein is also provided.

A semiconductor device includes; a first fin vertically protruding from a substrate and extending in a first horizontal direction, a second fin vertically protruding from the substrate, an isolation layer contacting side surfaces of the first fin and the second fin, a first lower barrier layer on the first fin, a second lower barrier layer on the second fin, source/drain regions spaced apart in the first horizontal direction on the first lower barrier layer, channel layers disposed between the source/drain regions and vertically spaced apart on the first barrier layer, a gate structure intersecting the first lower barrier layer, surrounding each of the channel layers, and extending in a second horizontal direction, an upper barrier layer on the second lower barrier layer, and first semiconductor layers and second semiconductor layers stacked on the upper barrier layer.

Provided are electronic devices and methods of manufacturing the same. An electronic device may include a substrate, a gate electrode on the substrate, a ferroelectric layer between the substrate and the gate electrode, and a carbon layer between the substrate and the ferroelectric layer. The carbon layer may have an sp.sup.2 bonding structure.

Embodiments disclosed herein include semiconductor devices and methods of forming such semiconductor devices. In an embodiment, a semiconductor device comprises a semiconductor channel, a source region adjacent to the semiconductor channel, and a drain region adjacent to the semiconductor channel. In an embodiment, the source region and the drain region each comprise a trench, a conformal silicide lining the trench, and a binary metallic alloy filling the trench.

A device includes a substrate, a gate structure, a source/drain region, a first silicide layer, a second silicide layer and a contact. The gate structure wraps around at least one vertical stack of nanostructure channels. The source/drain region abuts the gate structure. The first silicide layer includes a first metal component on the source/drain region. The second silicide layer includes a second metal component different than the first metal component, and is on the first silicide layer. The contact is on the second silicide layer.

A method includes forming first and second semiconductor fins protruding from a substrate. Each of the first and second semiconductor fins includes a stack of alternating channel layers and non-channel layers. The method also includes forming a dielectric helmet between and protruding from the first and the second semiconductor fins, forming a dummy gate stack over the dielectric helmet, patterning the dummy gate stack to expose a portion of the dielectric helmet, removing the exposed portion of the dielectric helmet, and forming a metal gate structure, such that a remaining portion of the dielectric helmet separates the metal gate structure between the first and the second semiconductor fins. The method also includes forming a contact feature over a portion of the metal gate structure. A sidewall of the contact feature is between one of the semiconductor fins and the remaining portion of the dielectric helmet.