A silicon carbide semiconductor device includes a silicon carbide substrate, a first electrode, and a second electrode. The silicon carbide substrate has a first main surface, a second main surface, a first impurity region, a second impurity region, and a third impurity region. The first electrode is in contact with each of the second impurity region and the third impurity region on the first main surface. The second electrode is in contact with the first impurity region on the second main surface. The second impurity region includes a first region and a second region disposed between the first region and the second main surface and in contact with the first region. An impurity concentration of the first region is more than or equal to 6×10.sup.16 cm.sup.−3.

A super-junction device and a method of fabricating such a device are disclosed, in which a pillar of a second conductivity type situated at an interface between a transition region and a core region is narrowed in width across at least an upper thickness thereof, thereby reducing peak electric field strength in the transition region, increasing voltage endurance of the transition region and preventing the occurrence of avalanche breakdown first in the transition region. Additionally, a dopant ion concentration profile increasing in the direction from the transition region to the core region is created across upper portions of some pillars of the second conductivity type in the core region, which increases the presence of the dopant of the second conductivity type around the surface of the core region and thus stops a vertical electric field before it can reach wells of the second conductivity type. That is, an effective epitaxial thickness of the core region is reduced, which results in lower voltage endurance thereof. In this way, it is ensured that avalanche breakdown occurs first in the core region, resulting in improved EAS performance.

A semiconductor device having a super junction and a method of manufacturing the semiconductor device capable of obtaining a high breakdown voltage are provided, whereby charge balance of the super junction is further accurately controlled in the semiconductor device that is implemented by an N-type pillar and a P-type pillar. The semiconductor device includes a semiconductor substrate; and a blocking layer including a first conductive type pillar and a second conductive type pillar that extend in a vertical direction on the semiconductor substrate and that are alternately arrayed in a horizontal direction, wherein, in the blocking layer, a density profile of a first conductive type dopant may be uniform in the horizontal direction, and the density profile of the first conductive type dopant may vary in the vertical direction.

A semiconductor device includes a composite pn-junction structure in a semiconductor substrate, wherein the composite pn-junction structure has a first junction grading coefficient m.sub.1, with m.sub.1≥0.50. The composite pn-junction structure includes a first partial pn-junction structure and a second partial pn-junction structure, wherein the first partial pn-junction structure has a first partial junction grading coefficient m.sub.11, and wherein the second partial pn-junction structure has a second partial junction grading coefficient m.sub.12. The first partial junction grading coefficient m.sub.11 is different to the second partial junction grading coefficient m.sub.12, with m.sub.11≠m.sub.12. At least one of the first and second partial junction grading coefficients m.sub.11, m.sub.12 is greater than 0.50, with m.sub.11 and/or m.sub.12>0.50. The first junction grading coefficient m.sub.1 of the composite pn-junction structure is based on a combination of the first and second partial junction grading coefficients m.sub.11, m.sub.12.

A semiconductor device includes a work piece comprising a first material, a first side, a second side opposite to the first side, and a first coefficient of thermal expansion (first CTE). Recesses extend into the work piece from the first side and includes a pattern. A second material having a second CTE is within the recesses and is over the first material between the recesses; and A third material having a third CTE is over one of the second side or the second material. The third CTE and the second CTE are different than the first CTE.

This disclosure provides a diode including a semiconductor region having at least one two-dimensional carrier channel of a first conductivity type. The diode also includes a plurality of sidewalls exposed in the semiconductor region defining at least one trench extending through the at least one two-dimensional carrier channel and a material of a second conductivity type, the second conductivity type being the other of the n-type and the p-type conductivity, disposed on the plurality of sidewalls and in contact with the at least one two-dimensional carrier channel. The diode also includes an anode material in contact with at least a portion of the semiconductor region and in contact with at least a portion of the material of the second conductivity type, and a cathode material in contact with the at least one two-dimensional carrier channel.

The quantum device comprises a transmission structure, wherein based on its geometrical arrangement, interference and quantum collapse, the transmission structure is designed such that quantum waves emitted by at least two bodies, for example, by thermal excitation, are passed preferentially to a subset of these bodies, without the need for a magnetic field to be applied.

The Rds*Cgd figure of merit (FOM) of a laterally diffused metal oxide semiconductor (LDMOS) transistor is improved by forming the drain drift region with a number of dopant implants at a number of depths, and forming a step-shaped back gate region with a number of dopant implants at a number of depths to adjoin the drain drift region.

A high electron mobility transistor includes a substrate. A first III-V compound layer is disposed on the substrate. A second III-V compound layer is embedded within the first III-V compound layer. A P-type gallium nitride gate is embedded within the second III-V compound layer. A gate electrode is disposed on the second III-V compound layer and contacts the P-type gallium nitride gate. A source electrode is disposed at one side of the gate electrode. A drain electrode is disposed at another side of the gate electrode.

A semiconductor device includes a semiconductor layer of a first conductivity type having a first main surface at one side and a second main surface at another side, a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer, a trench source structure including a source trench formed deeper than the gate trench and across an interval from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a deep well region of a second conductivity type formed in a region of the semiconductor layer along the source trench, a ratio of a depth of the trench source structure with respect to a depth of the trench gate structure being not less than 1.5 and not more than 4.0, a body region of the second conductivity type formed in a region of a surface layer portion of the first main surface of the semiconductor layer between the gate trench and the source trench, a source region of the first conductivity type formed in a surface layer portion of the body region, and a drain electrode connected to the second main surface of the semiconductor layer.