A semiconductor device has transistor portions and diode portions. The transistor portions have a semiconductor substrate of a first conductivity type, a first semiconductor region of a second conductivity type, second semiconductor regions of the first conductivity type, gate insulating films, gate electrodes, a first semiconductor layer of the first conductivity type, a third semiconductor region of the second conductivity type, a first electrode, and a second electrode. The diode portions have the semiconductor substrate, the first semiconductor region, the first semiconductor layer, a fourth semiconductor region of the first conductivity type, the first electrode, and the second electrode. The first semiconductor layer has a predetermined region, a depth of the predetermined region from a second main surface of the semiconductor substrate is greater than a depth of a region of the first semiconductor layer excluding the predetermined region, from the second main surface of the semiconductor substrate.

An edge delimits a semiconductor body in a direction parallel to a first side of the semiconductor body. A peripheral area is arranged between the active area and edge. A first semiconductor region of a first conductivity type extends from the active area into the peripheral area. A second semiconductor region of a second conductivity type forms a pn-junction with the first semiconductor region. A first edge termination region of the second conductivity type arranged at the first side adjoins the first semiconductor region, between the second semiconductor region and edge. A second edge termination region of the first conductivity type arranged at the first side and between the first edge termination region and edge has a varying concentration of dopants of the first conductivity type which increases at least next to the first edge termination region substantially linearly with an increasing distance from the first edge termination region.

The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate of a first semiconductor material; shallow trench isolation (STI) features formed in the semiconductor substrate; and a fin-like active region of a second semiconductor material epitaxy grown on the semiconductor substrate. The first semiconductor material has a first lattice constant and the second semiconductor material has a second lattice constant different from the first lattice constant. The fin-like active region further includes fluorine species.

A FinFET including a substrate, a plurality of insulators and a gate stack is provided. The substrate comprises a plurality of trenches and at least one semiconductor fin between the trenches, wherein the semiconductor fin comprises at least one groove, and the at least one groove is located on a top surface of the semiconductor fin. The insulators are disposed in the trenches. The gate stack partially covers the semiconductor fin, the at least one groove and the insulators.

A structure includes a field isolation region in a high resistivity substrate, a compensation implant region under the field isolation region in the high resistivity substrate, where the compensation implant region is configured to substantially eliminate a parasitic p-n junction under the field isolation region. The parasitic p-n junction is formed between trapped charges in the field isolation region and the high resistivity substrate. The compensation implant region includes a charge of a first conductivity type to compensate a parasitic charge of a second conductivity type under the field isolation region. The compensation implant region is configured to improve linearity of RF signals propagating through a metallization layer over the field isolation region. The structure further includes a deep trench extending through the field isolation region and the compensation implant region, and a damaged region adjacent the deep trench.

A tunneling field effect transistor, comprising a gate electrode layer, a gate dielectric layer, a source region, a connected region and a drain region, wherein the source region comprises a first source region and a second source region, the second source region comprising an inner layer source region and an outer layer source region. The connected region comprises an expansion region and a high-resistance region. The doping types of materials of the inner layer source and the outer layer source region are opposite, and the forbidden bandwidth of the material of the inner layer source region is less than that of the outer layer source region. The contact surface formed by way of covering the inner layer source region by the outer layer source region is a curved surface. Since a contact surface of an outer layer source region and an inner layer source region of a tunneling field effect transistor is of a curved surface structure, the contact area of the outer layer source region and the inner layer source region is increased, and the probability of tunneling of a carrier through the contact surface is increased. Therefore, the On-state current is increased, thereby having a good current drive capability.

According to some embodiments in this application, a method for making a JFET device is disclosed in the following steps: forming a substrate; performing ion implantation on the first region and the second region of the substrate to form a deep N-type well, wherein the deep N-type well is formed with at least two sub-wells region; forming a field oxide in the second region; forming a P-type well in one side of the sub-well in the deep N-type well; performing P-type ion implantation on the third region and the fourth region to respectively form a first P-type heavily doped region and a second P-type heavily doped region; and performing N-type ion implantation on the fifth region, the sixth region, and the seventh region to respectively form a first N-type heavily doped region, a second N-type heavily doped region, and a third N-type heavily doped region.

An ESD protection apparatus includes a semiconductor substrate, a first gate structure, a first doping region, a second doping region and a third doping region. The semiconductor substrate has a doping well with a first conductivity one end of which is grounded. The first gate structure is disposed on the doping well. The first doping region having a second conductivity, is disposed in the doping well and adjacent to the first gate structure, and is electrically connected to a pad. The second doping region having the second conductivity is disposed in the doping well and adjacent to the first gate structure. The third doping region having the first conductivity is disposed in the doping well and forms a P/N junction interface with the second doping region, wherein the second doping region and the third doping region respectively have a doping concentration substantially greater than that of the doping well.

A fin structure for a semiconductor device, such as a FinFET structure, has first and second semiconductor layers and an air gap between the layers. The air gap may prevent current leakage. A FinFET device may be manufactured by first recessing and then epitaxially re-growing a source/drain fin, with the regrowth starting over a tubular air gap.

A semiconductor device having a low on-voltage of IGBT and a small reverse recovery current of the diode is provided. The semiconductor device includes a semiconductor substrate having a gate trench and a dummy trench. The semiconductor substrate includes emitter, body, barrier and pillar regions between the gate trench and the dummy trench. The emitter region is an n-type region being in contact with the gate insulating film and exposed on a front surface. The body region is a p-type region being in contact with the gate insulating film at a rear surface side of the emitter region. The barrier region is an n-type region being in contact with the gate insulating film at a rear surface side of the body region and in contact with the dummy insulating film. The pillar region is an n-type region connected to the front surface electrode and the barrier region.