In one embodiment, the semiconductor devices relate to using one or more super-junction trenches for termination.

Diodes and fabrication methods thereof are presented. The diodes include, for instance: a first semiconductor region disposed at least partially within a substrate, the first semiconductor region having a first conductivity type; and a second semiconductor region disposed at least partially within the first semiconductor region, the second semiconductor region having a second conductivity type, wherein the first semiconductor region separates the second semiconductor region from the substrate. In one embodiment, the substrate and the first semiconductor region have a sigma-shaped boundary. In another embodiment, the substrate and the first semiconductor region have U-shaped boundary. In a further embodiment, the first semiconductor region comprises an alloy of a first material and a second material, where the concentration of the second material varies from a maximum to a minimum, where the first semiconductor region adjacent to the second semiconductor region has the minimum of the concentration of the second material.

A silicon carbide semiconductor device includes: a substrate; a drift layer over the substrate; a base region over the drift layer; multiple source regions over an upper layer portion of the base region; a contact region over the upper layer portion of the base region between opposing source regions; multiple trenches from a surface of each source region to a depth deeper than the base region; a gate electrode on a gate insulating film in each trench; a source electrode electrically connected to the source regions and the contact region; a drain electrode over a rear surface of the substrate; and multiple electric field relaxation layers in the drift layer between adjacent trenches. Each electric field relaxation layer includes: a first region at a position deeper than the trenches; and a second region from a surface of the drift layer to the first region.

A semiconductor device includes transistor cells in a semiconductor portion, wherein the transistor cells are electrically connected to a gate metallization, a source electrode and a drain electrode. In one example, the semiconductor device further includes a doped region in the semiconductor portion. The doped region is electrically connected to the source electrode. A resistance of the doped region has a negative temperature coefficient. An interlayer dielectric separates the gate metallization from the doped region. A drain structure in the semiconductor portion electrically connects the transistor cells with the drain electrode and forms a pn junction with the doped region.

A power metal-oxide-semiconductor (MOS) device is provided. The power MOS device is formed on a semiconductor substrate and includes an active region and a breakdown generated region. The active region includes a plurality of P-type doping regions and a plurality of N-type doping region alternatively arrayed between a source electrode and a drain electrode, and also includes a plurality of gate structures for controlling the conductive state of the active region. The breakdown generated region includes at least one P-type doping region and at least one N-type doping region alternatively arrayed between a source electrode and a drain electrode, and the breakdown voltage of the breakdown generated region is smaller than that of the active region.

A compound semiconductor device includes a compound semiconductor layer, a gate electrode disposed above the compound semiconductor layer, and source and drain electrodes disposed above the compound semiconductor layer with the gate electrode between the source and drain electrodes, wherein the compound semiconductor layer has a groove in a surface thereof at least between the source electrode and the gate electrode in a region between the source electrode and the drain electrode, the groove gradually deepened toward the source electrode.

A conventional DRAM needs to be refreshed at an interval of several tens of milliseconds to hold data, which results in large power consumption. In addition, a transistor therein is frequently turned on and off; thus, deterioration of the transistor is also a problem. These problems become significant as the memory capacity increases and transistor miniaturization advances. A transistor is provided which includes a wide-gap semiconductor and has a trench structure including a trench for a gate electrode and a trench for element isolation. Even when the distance between a source electrode and a drain electrode is decreased, the occurrence of a short-channel effect can be suppressed by setting the depth of the trench for the gate electrode as appropriate.

A monolithic, vertical, planar semiconductor structure with a number diodes having different intrinsic regions is described. The diodes have intrinsic regions of different thicknesses as compared to each other. In one example, the semiconductor structure includes an N-type silicon substrate, an intrinsic layer formed on the N-type silicon substrate, and a dielectric layer formed on the intrinsic layer. A number of openings are formed in the dielectric layer. Multiple anodes are sequentially formed into the intrinsic layer through the openings formed in the dielectric layer. For example, a first P-type region is formed through a first one the openings to a first depth into the intrinsic layer, and a second P-type region is formed through a second one of the openings to a second depth into the intrinsic layer. Additional P-type regions can be formed to other depths.

A semiconductor device has transistor portions and diode portions. The transistor portions have a semiconductor substrate of a first conductivity type, a first semiconductor region of a second conductivity type, second semiconductor regions of the first conductivity type, gate insulating films, gate electrodes, a first semiconductor layer of the first conductivity type, a third semiconductor region of the second conductivity type, a first electrode, and a second electrode. The diode portions have the semiconductor substrate, the first semiconductor region, the first semiconductor layer, a fourth semiconductor region of the first conductivity type, the first electrode, and the second electrode. A first depth of the first semiconductor layer from the back surface of the semiconductor substrate in the transistor portions is greater than a second depth of the first semiconductor layer from the back surface of the semiconductor substrate in the diode portions.

A non-uniform base width bipolar junction transistor (BJT) device includes: a semiconductor substrate, the semiconductor substrate having an upper surface; and a BJT device, the BJT device comprising a collector region, a base region, and an emitter region positioned in the semiconductor substrate, the base region being positioned between the collector region and the emitter region; the base region comprising a top surface and a bottom surface, wherein a first width of the top surface of the base region in a base width direction of the BJT device is greater than a second width of the bottom surface of the base region in the base width direction of the BJT device.