A silicon-based quantum device is provided. The device comprises: a first metallic structure (501); a second metallic structure (502) laterally separated from the first metallic structure; and an L-shaped elongate channel (520) defined by the separation between the first and second metallic structures; wherein the elongate channel has a vertex (505) connecting two elongate parts of the elongate channel. The device further comprises: a third metallic structure (518), mediator gate, positioned in the elongate channel; a fourth metallic structure (531) forming a first barrier gate, arranged at a first end of the third metallic structure; and a fifth metallic structure (532) forming a second barrier gate arranged at a second end of the third metallic structure. The first, second, third, fourth and fifth metallic structures are configured for connection to first, second, third, fourth and fifth electric potentials respectively. The first, second, fourth and fifth electric potentials are controllable to define an electrical potential well to confine quantum charge carriers in an elongate quantum dot beneath the elongate channel. The fourth and fifth electric potentials and the position of the fourth and fifth metallic structures define first and second ends of the elongate channel respectively. The width of the electrical potential well is defined by the position of the first and second metallic structures and their corresponding electric potentials; and the length of the electrical potential well is defined by the position of the fourth and fifth metallic structures and their corresponding electric potentials. The third electric potential is controllable to adjust quantum charge carrier energy levels in the electrical potential well.

A lateral transistor tile is formed with first and second collector regions that longitudinally span first and second sides of the transistor tile; and a base region and an emitter region that are between the first and second collector regions and are both centered on a longitudinal midline of the transistor tile. A base-collector current, a collector-emitter current, and a base-emitter current flow horizontally; and the direction of the base-emitter current is perpendicular to the direction of the base-collector current and the collector-emitter current. Lateral BJT transistors having a variety of layouts are formed from a plurality of the tiles and share common components thereof.

A semiconductor device comprises: a substrate; a well region provided in the substrate, having a second conductivity type; source regions having a first conductivity type; body tile regions having the second conductivity type, the source regions and the body tie regions being alternately arranged in a conductive channel width direction so as to form a first region extending along the conductive channel width direction, and a boundary where the edges of the source regions and the edges of the body tie regions are alternately arranged being formed on two sides of the first region; and a conductive auxiliary region having the first conductivity type, provided on at least one side of the first region, and directly contacting the boundary, a contact part comprising the edge of at least one source region on the boundary and the edge of at least one body tie region on the boundary.

A semiconductor high-voltage device includes a semiconductor substrate; a high-voltage well in the semiconductor substrate; a drift region in the high-voltage well; a recessed channel region adjacent to the drift region; a heavily doped drain region in the drift region and spaced apart from the recessed channel; an isolation structure between the recessed channel region and the heavily doped drain region in the drift region; a buried gate dielectric layer on the recessed channel region, wherein the top surface of the buried gate dielectric layer is lower than the top surface of the heavily doped drain region; and a gate on the buried gate dielectric layer.

Aspects of the present disclosure include one or more semiconductor electrostatic discharge protection devices. At least one embodiment includes a semiconductor electrostatic discharge device with one or more fingers divided into two segments with alternating p-diffusion and n-diffusion regions, with each region being associated with at least one of a portion of a diode and/or silicon-controlled rectifier (SCR).

A 3D semiconductor device including: a first level including a plurality of first metal layers; a second level, where the second level overlays the first level, where the second level includes at least one single crystal silicon layer, where the second level includes a plurality of transistors, where each transistor of the plurality of transistors includes a single crystal channel, where the second level includes a plurality of second metal layers, where the plurality of second metal layers include interconnections between the transistors of the plurality of transistors, and where the second level is overlaid by a first isolation layer; and a connective path between the plurality of transistors and the plurality of first metal layers, where the connective path includes a via disposed through at least the single crystal silicon layer, and where the via includes contact with at least one of the plurality of transistors.

In a semiconductor device according to the technology disclosed in the present specification, a temperature detection region is provided with a diffusion layer of a second conductivity type provided on a surface layer of a drift layer of a first conductivity type, a well layer of a first conductivity type provided on a surface layer of the diffusion layer and electrically connected to an anode electrode, and a cathode layer of a first conductivity type provided on a surface layer of the well layer and electrically connected to a cathode electrode.

A 3D semiconductor device including: a first level including a single crystal silicon layer and a plurality of first transistors, the plurality of first transistors each including a single crystal channel; a first metal layer overlaying the plurality of first transistors; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; a second level is disposed above the third metal layer, where the second level includes a plurality of second transistors; a fourth metal layer disposed above the second level; and a connective path between the fourth metal layer and either the third metal layer or the second metal layer, where the connective path includes a via disposed through the second level, where the via has a diameter of less than 800 nm and greater than 5 nm, and where at least one of the plurality of second transistors includes a metal gate.

A semiconductor structure is provided, and the semiconductor structure includes a substrate, and an active area is defined thereon, a gate structure spanning the active area, wherein the overlapping range of the gate structure and the active area is defined as an overlapping region, and the overlapping region includes four corners, and at least one salicide block covering the four corners of the overlapping region.

A semiconductor device includes a substrate, a first isolation structure, a second isolation structure and a dummy pattern. The substrate includes a first part surrounding a second part at a top view. The first isolation structure is disposed between the first part and the second part, to isolate the first part from the second part. The second isolation structure is disposed at at least one corner of the first part. The dummy pattern is disposed on the second isolation structure. The present invention also provides a method of forming said semiconductor device.