Provided is a semiconductor device having transistor and diode sections. The semiconductor device comprises: a gate metal layer provided above the upper surface of a semiconductor substrate; an emitter electrode provided above the upper surface of the semiconductor substrate; a first conductivity-type emitter region provided on the semiconductor substrate upper surface side in the transistor section; a gate trench section, which is provided on the semiconductor substrate upper surface side in the transistor section, is electrically connected to the gate metal layer, and is in contact with the emitter region; an emitter trench section, which is provided on the semiconductor substrate upper surface side in the diode section, and is electrically connected to the emitter electrode; and a dummy trench section, which is provided on the semiconductor substrate upper surface side, is electrically connected to the gate metal layer, and is not in contact with the emitter region.

A method for manufacturing an IGBT device includes: forming a source of the IGBT device in a substrate, wherein the substrate is an MCZ substrate; performing annealing processing on the substrate, wherein a layer of oxide is formed on the surface of the source during an annealing process; forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer is comprised of a silicon nitride layer, a first type oxide layer, and a second type oxide layer, and a material used to form the first type oxide layer is different from a material used to form the second type oxide layer; and performing nitrogen annealing processing on the substrate.

A semiconductor device includes first and third semiconductor layers of a first conductivity type, and second, fourth and fifth semiconductor layers of a second conductivity type. The first semiconductor layer is provided on the fifth semiconductor layer. The second semiconductor layer is provided on the first semiconductor layer. The third and fourth semiconductor layers are arranged along the second semiconductor layer. In a plane parallel to an upper surface of the second semiconductor layer, the fourth semiconductor layer has a surface area greater than a surface area of the third semiconductor layer. The device further includes first to third electrodes, and first control electrode. The first to third electrodes are electrically connected to the third to fifth semiconductor layers, respectively. The first control electrode is provided in a first trench extending into the first semiconductor layer from an upper surface of the third semiconductor layer.

Disclosed herein are tunneling field effect transistors (TFETs), and related methods and computing devices. In some embodiments, a TFET may include: a first source/drain material having a p-type conductivity; a second source/drain material having an n-type conductivity; a channel material at least partially between the first source/drain material and the second source/drain material, wherein the channel material has a first side face and a second side face opposite the first side face; and a gate above the channel material, on the first side face, and on the second side face.

Thyristor semiconductor device comprising an anode region, a first base region and a second base region having opposite types of conductivity, and a cathode region, all superimposed along a vertical axis.

Electrical overstress protection for high speed interfaces are disclosed. In certain embodiments, a semiconductor die with bidirectional protection against electrical overstress is provided. The semiconductor die includes a first pad, a second pad, a forward protection silicon controlled rectifier (SCR) electrically connected between the first pad and the second pad and configured to activate in response to electrical overstress that increases a voltage of the first pad relative to a voltage of the second pad, and a reverse protection SCR electrically connected in parallel with the forward protection SCR between the first pad and the second pad and configured to activate in response to electrical overstress that decreases the voltage of the first pad relative to the voltage of the second pad.

A semiconductor device includes a semiconductor layer having a first principal surface on one side thereof and a second principal surface on the other side thereof, a channel region of a first conductivity type formed at a surface layer portion of the first principal surface of the semiconductor layer, an emitter region of a second conductivity type formed at a surface layer portion of the channel region in the semiconductor layer, a drift region of the second conductivity type formed in a region of the second principal surface side with respect to the channel region in the semiconductor layer so as to be electrically connected to the channel region, a collector region of the first conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically connected to the drift region, a cathode region of the second conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically connected to the drift region and including a continuously laid around line-shaped pattern, and a gate electrode formed at the first principal surface side of the semiconductor layer so as to face the channel region across an insulating film.

Examples of a semiconductor device includes a transistor region formed in a semiconductor substrate having a first conductivity type drift layer, and a diode region formed to be adjacent to the transistor region in the semiconductor substrate, wherein the diode region has a second conductivity type anode layer formed on the drift layer and a first conductivity type cathode layer formed on the lower side of the drift layer, and the cathode layer has an adjacent region contacting the transistor region, the adjacent region having a depth, from a lower surface of the semiconductor substrate, which becomes shallower toward the transistor region and having first conductivity type impurity concentration which decreases toward the transistor region.

Provided is an IGBT power device. The device includes: a p-type collector region; an n-type drift region located above the p-type collector region; multiple first grooves, where a second groove is provided below each of the multiple first grooves; a gate structure located in the first groove and the second groove; a p-type body region located between two adjacent first grooves; an n-type emitter region located in the p-type body region; and an n-type hole charge blocking region located between two adjacent second grooves.

A semiconductor device includes a semiconductor layer, a crystal defect region formed in the semiconductor layer, and an insulating layer formed on the semiconductor layer, composed of an insulator containing silicon, and including, in the insulator, an Si—H bond in which a dangling bond of silicon atom is hydrogen-terminated.