H01L29/0895

Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

Tunnel field effect transistors

Tunnel field effect devices and methods of fabricating tunnel field effect devices are described. In one embodiment, the semiconductor device includes a first drain region of a first conductivity type disposed in a first region of a substrate, a first source region of a second conductivity type disposed in the substrate, the second conductivity type being opposite the first conductivity type, a first channel region electrically coupled between the first source region and the first drain region, the first source region underlying a least a portion of the first channel region, and a first gate stack overlying the first channel region.

ENERGY-FILTERED COLD ELECTRON DEVICES AND METHODS
20190214488 · 2019-07-11 ·

Energy-filtered cold electron devices use electron energy filtering through discrete energy levels of quantum wells or quantum dots that are formed through band bending of tunneling barrier conduction band. These devices can obtain low effective electron temperatures of less than or equal to 45K at room temperature, steep electrical current turn-on/turn-off capabilities with a steepness of less than or equal to 10 mV/decade at room temperature, subthreshold swings of less than or equal to 10 mV/decade at room temperature, and/or supply voltages of less than or equal to 0.1 V.

InN TUNNEL JUNCTION CONTACTS FOR P-CHANNEL GaN
20190207003 · 2019-07-04 ·

Methods and apparatus for semiconductor manufacture are disclosed. An example apparatus includes a Gallium Nitride (GaN) substrate; a p-type GaN region positioned on the GaN substrate; a p-type Indium Nitride (InN) region positioned on the GaN substrate and sharing an interface with the p-type GaN region; and a n-type Indium Gallium Nitride (InGaN) region positioned on the GaN substrate and sharing an interface with the p-type InN region.

Tunnel field-effect transistor (TFET) with lateral oxidation

A vertical-mode tunnel field-effect transistor (TFET) is provided with an oxide region that may be laterally positioned relative to a source region. The oxide region operates to reduce a tunneling effect in a tunnel region underlying a drain region, during an OFF-state of the TFET. The reduction in tunneling effect results in a reduction or elimination of a flow of OFF-state leakage current between the source region and the drain region. The TFET may have components made from group III-V compound materials.

Tunneling Enabled Feedback FET
20240213321 · 2024-06-27 ·

Example embodiments relate to tunneling enabled feedback field effect transistors (FETs). One example system includes a feedback field effect transistor. The feedback field effect transistor includes a source region. The feedback field effect transistor also includes a channel region. Additionally, the feedback field effect transistor includes a drain region. Further, the feedback field effect transistor includes a gate. The channel region is between the source region and the drain region. The source region, the channel region, and the drain region include a semiconductor material with a bandgap that is smaller than 0.9 eV. The source region or the drain region has a dopant concentration that is smaller than 5?10.sup.19 cm.sup.?3. The gate is positioned along the channel and isolated from the channel.

Double gate transistor device and method of operating

In accordance with an embodiment, a method includes switching on a transistor device by generating a first conducting channel by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel by driving a second gate electrode, wherein the second gate electrode is adjacent the first gate electrode in a current flow direction of the transistor device.

Energy-filtered cold electron devices and methods

Energy-filtered cold electron devices use electron energy filtering through discrete energy levels of quantum wells or quantum dots that are formed through band bending of tunneling barrier conduction band. These devices can obtain low effective electron temperatures of less than or equal to 45K at room temperature, steep electrical current turn-on/turn-off capabilities with a steepness of less than or equal to 10 mV/decade at room temperature, subthreshold swings of less than or equal to 10 mV/decade at room temperature, and/or supply voltages of less than or equal to 0.1 V.

Vertical transistor gated diode

After forming a trench extending through a sacrificial gate layer to expose a surface of a doped bottom semiconductor layer, a diode including a first doped semiconductor segment and a second doped semiconductor segment having a different conductivity type than the first doped semiconductor segment is formed within the trench. The sacrificial gate layer that laterally surrounds the first doped semiconductor segment and the second doped semiconductor segment is subsequently replaced with a gate structure to form a gated diode.

Homoepitaxial tunnel barriers with hydrogenated graphene-on-graphene for room temperature electronic device applications

A homoepitaxial, ultrathin tunnel barrier-based electronic device in which the tunnel barrier and transport channel are made of the same materialgraphene.