The present disclosure describes methods and epitaxial oxide devices with impact ionization. A method can comprise: applying a bias across a semiconductor structure using a first electrical contact and a second electrical contact; injecting a hot electron, from the first electrical contact, through a second semiconductor layer, and into a conduction band of a first epitaxial oxide material; and forming an excess electron-hole pair in an impact ionization region of the first semiconductor layer via impact ionization. The semiconductor structure can comprise: the first electrical contact; the first semiconductor layer with the first epitaxial oxide material with a first bandgap coupled to the first electrical contact; a second semiconductor layer with a second epitaxial oxide material with a second bandgap coupled to the first semiconductor layer; and a second electrical contact coupled to the second semiconductor layer, wherein the second bandgap is wider than the first bandgap.

A homoepitaxial, ultrathin tunnel barrier-based electronic device in which the tunnel barrier and transport channel are made of the same materialgraphene.

An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

After forming a trench extending through a sacrificial gate layer to expose a surface of a doped bottom semiconductor layer, a diode including a first doped semiconductor segment and a second doped semiconductor segment having a different conductivity type than the first doped semiconductor segment is formed within the trench. The sacrificial gate layer that laterally surrounds the first doped semiconductor segment and the second doped semiconductor segment is subsequently replaced with a gate structure to form a gated diode.

Structures and methods for a tunnel field-effect transistor (TFET). The TFET includes a gate electrode, a source region having a first conductivity type, a drain region having a second conductivity type opposite from the first conductivity type, and a and a dielectric layer separating the gate electrode from the source region and the drain region. The dielectric layer provides a channel region between the source region and the drain region. The channel region includes a relatively thin tunnel dielectric between the source region and the gate electrode and a relatively thick drift dielectric between the gate electrode and the drain region.

A homoepitaxial, ultrathin tunnel barrier-based electronic device in which the tunnel barrier and transport channel are made of the same materialgraphene.

A tunnel field-effect transistor device includes a p-type GaN source layer, an ntype GaN drain layer, and an interlayer interfaced between the source-layer and the drain layer. These devices employ polarization engineering in GaN/InN heterojunctions to achieve appreciable interband tunneling current densities. In one example, the interlayer includes an Indium Nitride (InN) layer. In one example, the interlayer includes a graded Indium gallium nitride layer and an InN layer. In one example, the interlayer may include a graded Indium gallium nitride (In.sub.xGa.sub.1-xN) layer and an Indium gallium nitride (InGaN) layer. In one example, the tunnel field-effect transistor device includes an in-line configuration. In one example, the tunnel field-effect transistor device includes a side-wall configuration. In one example, the tunnel field-effect transistor device includes a nanowire cylindrical gate-all-around geometry to achieve a high degree of gate electrostatic control.

A vertical-mode tunnel field-effect transistor (TFET) is provided with an oxide region that may be laterally positioned relative to a source region. The oxide region operates to reduce a tunneling effect in a tunnel region underlying a drain region, during an OFF-state of the TFET. The reduction in tunneling effect results in a reduction or elimination of a flow of OFF-state leakage current between the source region and the drain region. The TFET may have components made from group III-V compound materials.

The present disclosure describes a semiconductor structure that includes a substrate from an undoped semiconductor material and a fin disposed on the substrate. The fin includes a non-polar top surface and two opposing first and second polar sidewall surfaces. The semiconductor structure further includes a polarization layer on the first polar sidewall surface, a doped semiconductor layer on the polarization layer, a dielectric layer on the doped semiconductor layer and on the second polar sidewall surface, and a gate electrode layer on the dielectric layer and the first polarized sidewall surface.

The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, the techniques described herein relate to a transistor, including: a substrate including a first oxide material; an epitaxial oxide layer on the substrate including a second oxide material with a first bandgap; a gate layer on the epitaxial oxide layer, the gate layer including a third oxide material with a second bandgap, wherein the second bandgap is wider than the first bandgap; and electrical contacts. The second oxide material can include: one or two of Li, Ni, Al, Ga, Mg, and Zn; Ge; and O. The second oxide can also include (Ni.sub.xMg.sub.yZn.sub.1-x-y).sub.2GeO.sub.4 wherein 0x1 and 0y1. The electrical contacts can include: a source electrical contact coupled to the epitaxial oxide layer; a drain electrical contact coupled to the epitaxial oxide layer; and a first gate electrical contact coupled to the gate layer.