In accordance with an embodiment, a method includes switching on a transistor device by generating a first conducting channel by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel by driving a second gate electrode, wherein the second gate electrode is adjacent the first gate electrode in a current flow direction of the transistor device.

The present disclosure relates to a tunnel FET device with a steep sub-threshold slope, and a corresponding method of formation. In some embodiments, the tunnel FET device has a dielectric layer arranged over a substrate. A conductive gate electrode and a conductive drain electrode are arranged over the dielectric layer. A conductive source electrode contacts the substrate at a first position located along a first side of the conductive gate electrode. The conductive drain electrode is arranged at a second position located along the first side of the conductive gate electrode. By arranging the conductive gate electrode over the dielectric layer at a position laterally offset from the conductive drain electrode, the conductive gate electrode is able to generate an electric field that controls tunneling of minority carriers, which can change the effective barrier height of the tunnel barrier, and thereby improving a sub-threshold slope of the tunnel FET device.

A semiconductor component is disclosed. The semiconductor component can include: a semiconductor layer injected with a same type of dopant; a gate electrode formed above the semiconductor layer with a gate insulation film positioned in-between; a dielectric layer formed on the semiconductor layer at both sides of the gate electrode; and source/drain electrodes each formed on the dielectric layer.

An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

This disclosure provides thin film transistors (TFTs) including p-n hetero-junction structures. A p-n hetero-junction structure may include a junction between a narrow bandgap material and a wide bandgap material. The narrow bandgap material, which may be an oxide, nitride, selenide, or sulfide, is the active channel material of the TFT and may provide relatively high carrier mobility. The hetero-junction structures facilitate band-to-band tunneling and suppression of TFT off-currents. In various implementations, the TFTs may be formed on flexible substrates and have low temperature processing capabilities.

The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a barrier layer disposed above the substrate, and a dielectric layer disposed on the barrier layer and defining a first recess. The semiconductor device further includes a spacer disposed within the first recess and a gate disposed between a first portion of the spacer and a second portion of the spacer, wherein the gate defining a first recess.

An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

The present disclosure describes a semiconductor structure that includes a substrate from an undoped semiconductor material and a fin disposed on the substrate. The fin includes a non-polar top surface and two opposing first and second polar sidewall surfaces. The semiconductor structure further includes a polarization layer on the first polar sidewall surface, a doped semiconductor layer on the polarization layer, a dielectric layer on the doped semiconductor layer and on the second polar sidewall surface, and a gate electrode layer on the dielectric layer and the first polarized sidewall surface.

Some embodiments of the disclosure provide a semiconductor device. The semiconductor device comprises: a substrate; a first nitride semiconductor layer on the substrate; a second nitride semiconductor layer on the first nitride semiconductor layer and having a band gap larger than a band gap of the first nitride semiconductor layer; an intermediate layer disposed on the second nitride semiconductor layer; and a conductive structure disposed on the intermediate layer, wherein a first even interface is formed between the intermediate layer and the second nitride semiconductor layer.

A semiconductor device includes at least one active pattern on a substrate, at least one gate electrode intersecting the at least one active pattern, source/drain regions on the at least one active pattern, the source/drain regions being on opposite sides of the at least one gate electrode, and a barrier layer between at least one of the source/drain regions and the at least one active pattern, the barrier layer being at least on bottoms of the source/drain regions and including oxygen.