A lateral III-N device has a vertical gate module with III-N material orientated in an N-polar or a group-III polar orientation. A III-N material structure has a III-N buffer layer, a III-N barrier layer, and a III-N channel layer. A compositional difference between the III-N barrier layer and the III-N channel layer causes a 2DEG channel to be induced in the III-N channel layer. A p-type III-N body layer is disposed over the III-N channel layer in a source side access region but not over a drain side access region. A n-type III-N capping layer over the p-type III-N body layer. A source electrode that contacts the n-type III-N capping layer is electrically connected to the p-type III-N body layer and is electrically isolated from the 2DEG channel when the gate electrode is biased relative to the source electrode at a voltage that is below a threshold voltage.

A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a gate on the channel region.

Methods and apparatus for semiconductor manufacture are disclosed. An example apparatus includes a Gallium Nitride (GaN) substrate; a p-type GaN region positioned on the GaN substrate; a p-type Indium Nitride (InN) region positioned on the GaN substrate and sharing an interface with the p-type GaN region; and a n-type Indium Gallium Nitride (InGaN) region positioned on the GaN substrate and sharing an interface with the p-type InN region.

An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

A method of constructing an electrical contact including a contact element positioned between a first contact member and a second contact member. The method includes defining a transmission line model to represent operation of the electrical contact. The transmission line model indicates a contact resistance and a specific contact resistivity along a length of the contact element. The method includes determining a current flow profile of the contact element. The current flow profile is determined based on a current distribution using the transmission line model. The method includes determining one of: (i) a material, (ii) a thickness, and (iii) a geometry of the contact element based on the contact resistance and the current flow profile of the transmission line model. The method includes constructing the contact element positioned between the first contact member and the second contact member with the at least one of (i) the material, (ii) the thickness, and (iii) the geometry.

A lateral III-N device has a vertical gate module with III-N material orientated in an N-polar or a group-III polar orientation. A III-N material structure has a III-N buffer layer, a III-N barrier layer, and a III-N channel layer. A compositional difference between the III-N barrier layer and the III-N channel layer causes a 2DEG channel to be induced in the III-N channel layer. A p-type III-N body layer is disposed over the III-N channel layer in a source side access region but not over a drain side access region. A n-type III-N capping layer over the p-type III-N body layer. A source electrode that contacts the n-type III-N capping layer is electrically connected to the p-type III-N body layer and is electrically isolated from the 2DEG channel when the gate electrode is biased relative to the source electrode at a voltage that is below a threshold voltage.

An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

To stably form a low-resistance electrical coupling between a metal and a semiconductor.

An electrical coupling structure includes: a semiconductor layer; a metal layer; and an intermediate layer that is held between the semiconductor layer and the metal layer, and includes an insulating layer provided on the semiconductor layer side and a two-dimensional material layer provided on the metal layer side.

A semiconductor device includes a channel layer disposed over a substrate, a barrier layer disposed over the channel layer, a gate electrode disposed over the barrier layer, and a pair of source/drain electrodes disposed on opposite sides of the gate electrode. The pair of source/drain electrodes extend through at least portions of the barrier layer. The semiconductor device also includes a lining layer conformally disposed on bottom portions of the pair of source/drain electrodes.