In accordance with an embodiment, a method includes switching on a transistor device by generating a first conducting channel by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel by driving a second gate electrode, wherein the second gate electrode is adjacent the first gate electrode in a current flow direction of the transistor device.

A semiconductor device is proposed. The semiconductor device includes a group III-N semiconductor layer, an electrically insulating material layer located on the group III-N semiconductor layer, and a metal contact structure located on the electrically insulating material layer. An electrical resistance between the metal contact structure and the group III-N semiconductor layer through the electrically insulating material layer is smaller than 1*10.sup.7 for an area of 1 mm.sup.2. Further, semiconductor devices including a low resistance contact structure, radio frequency devices, and methods for forming semiconductor devices are proposed.

A semiconductor device includes a plurality of base layers. A tunneling layer is disposed on the plurality of base layers. A contact layer is disposed on the tunneling layer. An alloyed metal contact is annealed on to the contact layer. The alloyed metal contact forms a first region and a second region in the contact layer. The first region of the contact layer diffuses into the tunneling layer. The second region of the contact layer resides over the tunneling layer. The tunneling layer facilitates electron mobility of the second region.

A semiconductor device includes a channel layer disposed over a substrate, a barrier layer disposed over the channel layer, a gate electrode disposed over the barrier layer, and a pair of source/drain electrodes disposed on opposite sides of the gate electrode. The pair of source/drain electrodes extend through at least portions of the barrier layer. The semiconductor device also includes a lining layer conformally disposed on bottom portions of the pair of source/drain electrodes.

A lateral III-N device has a vertical gate module with III-N material orientated in an N-polar or a group-III polar orientation. A III-N material structure has a III-N buffer layer, a III-N barrier layer, and a III-N channel layer. A compositional difference between the III-N barrier layer and the III-N channel layer causes a 2DEG channel to be induced in the III-N channel layer. A p-type III-N body layer is disposed over the III-N channel layer in a source side access region but not over a drain side access region. A n-type III-N capping layer over the p-type III-N body layer. A source electrode that contacts the n-type III-N capping layer is electrically connected to the p-type III-N body layer and is electrically isolated from the 2DEG channel when the gate electrode is biased relative to the source electrode at a voltage that is below a threshold voltage.

The present disclosure describes a semiconductor structure that includes a substrate from an undoped semiconductor material and a fin disposed on the substrate. The fin includes a non-polar top surface and two opposing first and second polar sidewall surfaces. The semiconductor structure further includes a polarization layer on the first polar sidewall surface, a doped semiconductor layer on the polarization layer, a dielectric layer on the doped semiconductor layer and on the second polar sidewall surface, and a gate electrode layer on the dielectric layer and the first polarized sidewall surface.

Energy-filtered cold electron devices use electron energy littering through discrete energy levels of quantum wells or quantum dots that are formed through band bending of tunneling barrier conduction band. These devices can obtain low effective electron temperatures of less than or equal to 45K at room temperature, steep electrical current turn-on/turn-off capabilities with a steepness of less than or equal to 10 mV/decade at room temperature, subthreshold swings of less than or equal to 10 mV/decade at room temperature, and/or supply voltages of less than or equal to 0.1 V.

A FINFET may include a semiconductor fin, spaced apart source and drain regions in the semiconductor fin with a channel region extending therebetween, and at least one dopant diffusion blocking superlattice dividing at least one of the source and drain regions into a lower region and an upper region with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a gate on the channel region.

A semiconductor device may include a semiconductor layer, spaced apart source and drain regions in the semiconductor layer with a channel region extending therebetween, and at least one dopant diffusion blocking superlattice dividing at least one of the source and drain regions into a lower region and an upper region with the upper region having a same conductivity and higher dopant concentration than the lower region. The at least one dopant diffusion blocking superlattice comprising a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a gate on the channel region.

A semiconductor device includes a source region, a drain region, a core channel region, and a barrier layer. The core channel region is between the source region and the drain region, The barrier layer is between the core channel region and the drain region, The barrier layer is a graded doped barrier layer.