A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer.

A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

A composition of matter comprising a film on a graphitic substrate, said film having been grown epitaxially on said substrate, wherein said film comprises at least one group III-V compound or at least one group II-VI compound.

Electrostatic discharge (ESD) structures are provided. An ESD structure includes a semiconductor substrate, a first epitaxy region with a first type of conductivity over the semiconductor substrate, a second epitaxy region with a second type of conductivity over the semiconductor substrate, and a plurality of first semiconductor layers and a plurality of second semiconductor layers. The first semiconductor layers and the second semiconductor layers are alternatingly stacked over the semiconductor substrate and between the first and second epitaxy regions. Each of the first and second semiconductor layers has a first side contacting the first epitaxy region and a second side contacting the second epitaxy region, and the first side is opposite the second side.

A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

A three-dimensional polycrystalline semiconductor material provides a major ingredient forming individual crystalline grains having a nominal maximum grain diameter less than or equal to 50 nm, and a minor ingredient forming boundaries between the individual crystalline grains.

The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

A heterostructure for use in an electronic or optoelectronic device is provided. The heterostructure includes one or more composite semiconductor layers. The composite semiconductor layer can include sub-layers of varying morphology, at least one of which can be formed by a group of columnar structures (e.g., nanowires). Another sub-layer in the composite semiconductor layer can be porous, continuous, or partially continuous.

This invention includes multiple quantum well and quantum dot channel FETs, which can process multi-state/multi-bit logic, and multibit-bit inverters configured as static random-access memories (SRAMs). SRAMs can be implemented as flip-flops and registers. In addition, multiple quantum well and quantum dot channel structures are configured to function as multi-bit high-speed quantum dot (QD) random access memories (NVRAMs). Multi-bit Logic, SRAMs and QD-NVRAMs are spatially located on a chip, depending on the application, to provide a low-power consumption and high-speed hardware platform. The multi-bit logic, SRAM and register, and QD-NVRAM are implemented on a single chip in a CMOS-like platform for applications including artificial intelligence (AI) and machine learning.

A digital circuit includes at least one quantum wire resonant tunneling transistor that includes an emitter terminal, a base terminal, a collector terminal, an emitter region in connection with the emitter terminal, a base region in connection with the base terminal, a collector region in connection with the collector terminal, an emitter barrier region between the emitter region and the base region, and a collector barrier region between the collector region and the base region. At least one of the emitter region, the base region, and the collector region includes a plurality of metal quantum wires.