A sensor element including a diamond in which nitrogen-vacancy centers in a diamond crystal structure stabilize in a negative charge state. By ensuring that the diamond of the sensor element is n-type phosphorus-doped and contains nitrogen-vacancy centers in the crystal structure, the probability that nitrogen-vacancy centers in the diamond lattice are in a neutral state decreases, and the nitrogen-vacancy centers stabilize in a negative charge state.

The plurality of first control electrodes extend in a first direction in a planar view, the plurality of second control electrodes extend in a second direction in a planar view. A sum of lengths in the first direction of boundaries between the second semiconductor layer and the plurality of third semiconductor layers on a surface of the semiconductor substrate which faces the plurality of first control electrodes is set as a first gate total width. A sum of lengths in the second direction of boundaries between the fourth semiconductor layer and the plurality of fifth semiconductor layers on a surface of the semiconductor substrate which faces the plurality of second control electrodes is set as a second gate total width. A gate width ratio obtained by dividing the second gate total width by the first gate total width is equal to or higher than 1.0.

A semiconductor device of the present invention includes a gate electrode buried in a gate trench of a first conductivity-type semiconductor layer, a first conductivity-type source region, a second conductivity-type channel region, and a first conductivity-type drain region formed in the semiconductor layer, a second trench selectively formed in a source portion defined in a manner containing the source region in the surface of the semiconductor layer, a trench buried portion buried in the second trench, a second conductivity-type channel contact region selectively disposed at a position higher than that of a bottom portion of the second trench in the source portion, and electrically connected with the channel region, and a surface metal layer disposed on the source portion, and electrically connected to the source region and the channel contact region.

A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, formed with a gate trench at a surface side of the cell portion, and a gate electrode buried in the gate trench via a gate insulating film, forming a channel at a portion lateral to the gate trench at ON-time, the outer peripheral portion has a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, and the semiconductor device further includes a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion.

A higher-current device is implemented by increasing cross-sectional areas of terminals while securing solderability during mounting. The device makes securing of a creepage distance between terminals compatible with a reduction in package size. A semiconductor device 1 is provided with a package 2, a semiconductor circuit 3, a control circuit 6, a plurality of main terminals 7 and control terminals 8. Each main terminal 7 is configured of a plurality of subterminals S1, S2 and S3 arranged at mutually neighboring positions and projecting from the package 2. Distal end portions of the subterminals S1, S2 and S3 making up the same main terminal 7 are bent toward a mounting surface on which the semiconductor device 1 is mounted and the bending positions of the subterminals S1, S2 and S3 are configured to differ between the mutually neighboring subterminals S1 and S2, and subterminals S2 and S3.

The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode formed to come into contact with a surface of the semiconductor layer, and has a threshold voltage V.sub.th of 0.3 V to 0.7 V and a leakage current J.sub.r of 1×10.sup.−9 A/cm.sup.2 to 1×10.sup.−4 A/cm.sup.2 in a rated voltage V.sub.R.

A semiconductor device has a substrate and graphene with semiconducting properties or diamond region formed on the substrate. The graphene with semiconducting properties or diamond region is formed on or within the substrate using liquid-phase-epitaxy growth of graphene enabled by a catalytic alloy of Ni and Cu. The substrate can be silicon, silicon carbide, gallium arsenide, gallium nitride, germanium, or indium phosphide. A semiconductor component is formed over the graphene with semiconducting properties or diamond region and substrate. The semiconductor component can be a power MOSFET, IGBT, or CTIGBT with a gate structure formed over the substrate, source region adjacent to the gate structure, and drain region adjacent to the gate structure opposite the source region. The graphene with semiconducting properties or diamond region is formed under a gate of the MOSFET to reduce drain to source resistance, as well as providing radiation hardening for the device.

A semiconductor device according to the present disclosure includes a semiconductor substrate having an effective region and an ineffective region, an upper surface electrode layer provided on an upper surface of the semiconductor substrate and a rear surface electrode layer provided on a rear surface of the semiconductor substrate, wherein the semiconductor substrate includes a lifetime control layer that is provided in the effective region, a measurement layer provided at an upper surface side of the ineffective region and a crystal defect layer that is provided in the ineffective region, the upper surface electrode layer includes a plurality of measurement electrodes provided on the measurement layer, the measurement layer includes a conducting layer at least at a portion where the plurality of measurement electrodes are provided, and the crystal defect layer is provided between the plurality of measurement electrodes.

Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The system may include a diamond malarial having n-type donor atoms and a diamond lattice, wherein 0.16% of the donor atoms contribute conduction electrons with mobility greater than 770 cm2/Vs to the diamond lattice at 100 kPa and 300K. The method of fabricating diamond semiconductors may include the steps of selecting a diamond material having a diamond lattice; introducing a minimal amount of acceptor dopant atoms to the diamond lattice to create ion tracks; introducing substitutional dopant atoms to the diamond lattice through the ion tracks; and annealing the diamond lattice.

In some embodiments, a semiconductor structure can include: a diamond substrate having a surface conductive layer; a heavily doped region formed in the diamond substrate; and a metal contact positioned over the conductive surface layer such that a first portion of the heavily doped region is covered by the metal contact and a second portion of the heavily doped region is not covered by the metal contact.