The present disclosure relates to semiconductor structures and, more particularly, to a wafer with crystalline silicon and trap rich polysilicon layer and methods of manufacture. The structure includes: semiconductor-on-insulator (SOI) wafer composed of a lower crystalline semiconductor layer, a polysilicon layer over the lower crystalline semiconductor layer, an upper crystalline semiconductor layer over the polysilicon layer, a buried insulator layer over the upper crystalline semiconductor layer, and a top crystalline semiconductor layer over the buried insulator layer.

A semiconductor device includes a substrate, a device isolation layer on the substrate, the device isolation layer defining a first active pattern, a pair of first source/drain patterns on the first active pattern, the pair of first source/drain patterns being spaced apart from each other in a first direction, and each of the pair of first source/drain patterns having a maximum first width in the first direction, a first channel pattern between the pair of first source/drain patterns, a gate electrode on the first channel pattern and extends in a second direction intersecting the first direction, and a first amorphous region in the first active pattern, the first amorphous region being below at least one of the pair of first source/drain patterns, and having a maximum second width in the first direction that is less than the maximum first width.

A microelectronic module that includes a semiconductor carrier including a FET that comprises a serpentine gate electrode having an elongated gate width and gate width-to-gate length ratio in access of 100 wherein resistive, capacitive, and inductive elements are embedded within the structure of the serpentine gate electrode.

An embodiment includes an apparatus comprising: a thin film transistor (TFT) comprising: source and drain contacts; first and second gate contacts: a semiconductor material, comprising a channel, between the first and second gate contacts; and a first dielectric layer, between the first and second gate contacts, to fix charged particles. Other embodiments are described herein.

A thin film transistor includes: a bottom gate electrode; a bottom gate electrode insulating layer, a semiconducting active layer and a first insulating layer which are disposed on the bottom gate electrode in sequence; a source electrode and a drain electrode which are disposed at a side of the first insulating layer away from the bottom gate electrode; vias disposed in the first insulating layer at positions which correspond to the source electrode and the drain electrode respectively; and ohmic contact layers disposed on and covering the semiconducting active layer at positions corresponding to the vias respectively. Each of the source electrode and the drain electrode is in contact with a corresponding one of the ohmic contact layers through a corresponding one of the vias.

A semiconductor device includes a substrate; and a fin protruding from the substrate. The fin includes a first material and a second material. The fin includes a lower section, a middle section, and an upper section. The middle section has a smaller width at a middle portion than a width at lower and upper portions of the middle section. A concentration of the second material gradually decreases from the middle portion in upward and downward directions.

A display apparatus includes a substrate, a first thin film transistor on the substrate, the first thin film transistor including an active layer including a source region, a drain region, and a channel region between the source region and the drain region, and a display device on the substrate and electrically connected to the first thin film transistor. The source region, the drain region, and the channel region include a first dopant and a second dopant, the second dopant being different from the first dopant. A concentration of the first dopant in the channel region is less than a concentration of the first dopant in the source region and the drain region.

A semiconductor structure, and a method for forming the same includes an amorphous semiconductor layer in contact with a top surface of a channel fin extending vertically from a bottom source/drain located above a substrate. A hard mask memorization layer is formed directly above the amorphous semiconductor layer, portions of the amorphous semiconductor layer in contact with the top surface of the channel fin are recrystallized forming recrystallized regions. The amorphous semiconductor layer is selective removed and a second dielectric layer is deposited to form a top spacer. The hard mask memorization layer and the recrystallized regions are removed, and a first epitaxial region is formed above the channel fin followed by a second epitaxial region positioned above the first epitaxial region and between the second dielectric layer forming a top source/drain of the semiconductor structure.

A display apparatus includes a substrate, a first thin film transistor on the substrate, the first thin film transistor including an active layer including a source region, a drain region, and a channel region between the source region and the drain region, and a display device on the substrate and electrically connected to the first thin film transistor. The source region, the drain region, and the channel region include a first dopant and a second dopant, the second dopant being different from the first dopant. A concentration of the first dopant in the channel region is less than a concentration of the first dopant in the source region and the drain region.

Embodiments of a glass wafer for semiconductor fabrication processes are described herein. In some embodiments, a glass wafer includes: a glass substrate comprising: a top surface, a bottom surface opposing the top surface, and an edge surface between the top surface and the bottom surface; a first coating disposed atop the glass substrate, wherein the first coating is a doped crystalline silicon coating having a sheet-resistance of 100 to 1,000,000 ohm per square; and a second coating having one or more layers disposed atop the glass substrate, wherein the second coating comprises a silicon containing coating, wherein the glass wafer has an average transmittance (T) of less than 50% over an entire wavelength range of 400 nm to 1000 nm.