A monolithic power management module provides a chip carrier with surfaces, ground traces, signal and power interconnects; a three dimensional FET formed on the chip carrier to modulate currents through the carrier or on the carrier surface; a toroidal inductor or transformer coil with a ceramic magnetic core formed on the chip carrier adjacent to the FET and having a first winding connected to the FET, and a plurality of passive ceramic components formed on the chip carrier surface.

An apparatus includes a junction field-effect transistor (JFET) and a set of one or more serially-connected diodes. The JFET includes a first layer including silicon of a first conductivity type, a gate, and first and second terminals. The gate includes a second layer formed on the first layer and including intrinsic amorphous hydrogenated silicon, a third layer formed on the second layer and including amorphous hydrogenated silicon of a second conductivity type, and a conductive layer formed on the third layer. Each of the first and second terminals includes a fourth layer formed on the first layer, the fourth layer including crystalline hydrogenated silicon of the first conductivity type, and a conductive layer formed on the fourth layer. Each of the serially-connected diodes has first and second terminals, a first of the serially-connected diodes having the first terminal connected to the second terminal of the JFET.

A disclosed transistor structure includes a gate electrode, an active layer, a source electrode, a drain electrode, an insulating layer separating the gate electrode from the active layer, and a carrier modification device that reduces short channel effects by reducing carrier concentration variations in the active layer. The carrier modification device may include a capping layer in contact with the active layer that acts to increase a carrier concentration in the active layer. Alternatively, the carrier modification device may include a first injection layer in contact with the source electrode and the active layer separating the source electrode from the active layer, and a second injection layer in contact with the drain electrode and the active layer separating the drain electrode from the active layer. The first and second injection layers may act to reduce a carrier concentration within the active layer near the source electrode and the drain electrode.

According to an embodiment of a semiconductor device, the semiconductor device includes a semiconductor body having a main surface, the semiconductor body including a drift region of monocrystalline SiC, the drift region being of a first conductivity type, and a metallization arranged at the main surface. In a cross-section which is substantially orthogonal to the main surface, the semiconductor body further includes a contact region of the monocrystalline SiC directly adjoining the drift region and the metallization, and an anode region of a semiconductor material having a lower band-gap than the monocrystalline SiC. The contact region is of a second conductivity type. The anode region is in ohmic contact with the metallization and forms a heterojunction with the drift region.

An apparatus includes a junction field-effect transistor (JFET) and a set of one or more serially-connected diodes. The JFET includes a first layer including silicon of a first conductivity type, a gate, and first and second terminals. The gate includes a second layer formed on the first layer and including intrinsic amorphous hydrogenated silicon, a third layer formed on the second layer and including amorphous hydrogenated silicon of a second conductivity type, and a conductive layer formed on the third layer. Each of the first and second terminals includes a fourth layer formed on the first layer, the fourth layer including crystalline hydrogenated silicon of the first conductivity type, and a conductive layer formed on the fourth layer. Each of the serially-connected diodes has first and second terminals, a first of the serially-connected diodes having the first terminal connected to the second terminal of the JFET.

An apparatus includes transistor and a set of one or more serially-connected diodes coupled to the transistor. The transistor includes a gate, and first and second terminals. A first diode in the set of serially-connected diodes has a first terminal connected to the second terminal of the transistor. At least one of the diodes includes a first layer including silicon having a first type of carrier as its majority carrier, a first terminal, and a second terminal. The first terminal includes a second layer formed on the first layer, a third layer comprising amorphous hydrogenated silicon having a second type of carrier as its majority carrier formed on the second layer, and a conductive layer formed on the third layer. The second terminal includes a fourth layer comprising crystalline hydrogenated silicon of the first carrier type formed on the first layer, and a conductive layer formed on the fourth layer.

Disclosed herein are transistor amorphous interlayer arrangements, and related methods and devices. For example, in some embodiments, transistor amorphous interlayer arrangement may include a channel material and a transistor source/drain stack. The transistor source/drain stack may include a transistor electrode material configured to be a transistor source/drain contact, i.e. either a source contact or a drain contact of the transistor, and a doped amorphous semiconductor material disposed between the transistor electrode material and the channel material.

A layer of amorphous silicon is formed on a germanium-on-insulator substrate, or a layer of germanium is formed on a silicon-on-insulator substrate. An anneal is then performed which causes thermal mixing of silicon and germanium atoms within one of the aforementioned structures and subsequent formation of a silicon germanium-on-insulator material.

A layer of amorphous silicon is formed on a germanium-on-insulator substrate, or a layer of germanium is formed on a silicon-on-insulator substrate. An anneal is then performed which causes thermal mixing of silicon and germanium atoms within one of the aforementioned structures and subsequent formation of a silicon germanium-on-insulator material.

A single crystal semiconductor structure includes: an amorphous substrate; a single crystal semiconductor layer provided on the amorphous substrate; and a thin orienting film provided between the amorphous substrate and the single crystal semiconductor layer, wherein the thin orienting film is a single crystal thin film, and the thin orienting film has a non-zero thickness that is equal to or less than 10 times a critical thickness h.sub.c.