A semiconductor device includes a substrate, a semiconductor structure suspending over the substrate and comprising a source region, a drain region, and a channel region disposed between the source region and the drain region. The channel region includes a doped two-dimensional (2D) material layer comprising a first portion on an upper surface of the channel region. The semiconductor device also includes an interfacial layer surrounding the channel region including the first portion of the doped 2D material layer, and and a gate electrode surrounding the interfacial layer.

The present disclosure relates to a graphene spin transistor for all-electrical operation at room temperature and a logic gate using the graphene Rashba spin transistor. A graphene spin transistor of the present disclosure provides a graphene spin FET (Field Effect Transistor) for all-electrical operation at room temperature without a magnetic field or a ferromagnetic electrode by utilizing the Rashba-Edelstein effect in the graphene or the spin Hall effect of a TMDC (Transition Metal Dichalcogenide) material in order to replace CMOS transistors and extend Moore's Law, and further provides a logic gate using the graphene Rashba spin transistor.

A field effect transistor structure is disclosed. The field effect transistor structure includes: a fin-shaped channel protruding from a substrate and extending in one direction; a source electrode on one side of the fin-shaped channel; a drain electrode separated from the source electrode with the fin-shaped channel therebetween; a gate insulating film surrounding side and upper surfaces of the fin-shaped channel; a gate electrode on the gate insulating film; and a two-dimensional semiconductor material layer between the gate insulating film and the gate electrode.

An FET, a method for manufacturing such FET, and an integrated circuit are disclosed. The FET includes a substrate carrying a gate electrode, a gate dielectric layer, and a channel layer sequentially stacked on the substrate. An insulating layer, an etching stop layer, and a protective layer are stacked sequentially on the channel layer. Source and drain electrodes are also formed. A material of the channel layer includes a 2D material. The FET defines two through holes extending through the insulating layer, the etching stop layer, and the protection layer and the channel layer is exposed, the two through holes carry the source and drain electrodes to form a top or direct contact with the channel layer.

An electronic device including a two-dimensional material is provided. The electronic device may include a substrate; a metal layer on a partial region of the substrate; a two-dimensional material layer over the metal layer and an upper surface of the substrate; and an insertion layer between the metal layer and the two-dimensional material layer.

This application relates to a pellicle for extreme ultraviolet lithography and a manufacturing method thereof using the low-temperature direct growth method of multilayer graphene. In one aspect, the method includes forming an etch stopper on a substrate, forming a seed layer on the etch stopper, the seed layer including at least one of amorphous boron, BN, BCN, B.sub.4C, or Me-X (Me is at least one of Si, Ti, Mo, or Zr, and X is at least one of B, C, or N). The method may also include forming a metal catalyst layer on the seed layer; forming an amorphous carbon layer on the metal catalyst layer, and directly growing multilayer graphene on the seed layer through interlayer exchange between the metal catalyst layer and the amorphous carbon layer by performing a low-temperature heat treatment at 450° C. to 600° C.

An electronic device includes: a substrate including a source, a drain, and a channel between the source and the drain; a gate electrode arranged above the substrate and facing the channel, the gate electrode being apart from the channel in a first direction; and a ferroelectric thin film structure between the channel and the gate electrode, the ferroelectric thin film structure including a first ferroelectric layer, a crystallization barrier layer including a dielectric material, and a second ferroelectric layer, which are sequentially arranged from the channel in the first direction. The average of sizes of crystal grains of the first ferroelectric layer may be less than or equal to the average of sizes of crystal grains of the second ferroelectric layer, and owing to small crystal grains, dispersion of performance may be improved.

A method of manufacturing a vacuum tunneling device, the method including forming a tunnelling device on a substrate; forming an insulating interlayer on the substrate such that the insulating interlayer has an opening exposing the tunneling device; and performing a gradient deposition process in a vacuum chamber to form a sealing layer on the insulating interlayer such that the sealing layer fills an upper portion of the opening.

An embodiment memory device includes a drain electrode disposed on a semiconductor substrate, a channel region in contact with the drain electrode, a source electrode in contact with the channel region, and a floating gate region in contact with the source electrode and the drain electrode, the floating gate region including a nano-dot region including at least one nano-dot gate, wherein the drain electrode is overlapped with the nano-dot region, and wherein the nano-dot region is overlapped with the channel region.

A reinforced thin-film device (100, 200, 500) including a substrate (101) having a top surface for supporting an epilayer; a mask layer (103) patterned with a plurality of nanosize cavities (102, 102′) disposed on said substrate (101) to form a needle pad; a thin-film (105) of lattice-mismatched semiconductor disposed on said mask layer (103), wherein said thin-film (105) comprises a plurality of in parallel spaced semiconductor needles (104, 204) of said lattice-mismatched semiconductor embedded in said thin-film (105), wherein said plurality of semiconductor needles (104, 204) are substantially vertically disposed in the axial direction toward said substrate (101) in said plurality of nanosize cavities (102, 102′) of said mask layer (103), and where a lattice-mismatched semiconductor epilayer (106) is provided on said thin-film supported thereby.