An embodiment is a method including forming a raised portion of a substrate, forming fins on the raised portion of the substrate, forming an isolation region surrounding the fins, a first portion of the isolation region being on a top surface of the raised portion of the substrate between adjacent fins, forming a gate structure over the fins, and forming source/drain regions on opposing sides of the gate structure, wherein forming the source/drain regions includes epitaxially growing a first epitaxial layer on the fin adjacent the gate structure, etching back the first epitaxial layer, epitaxially growing a second epitaxial layer on the etched first epitaxial layer, and etching back the second epitaxial layer, the etched second epitaxial layer having a non-faceted top surface, the etched first epitaxial layer and the etched second epitaxial layer forming source/drain regions.

A circuit, including: a photodetector including a first readout terminal and a second readout terminal different than the first readout terminal; a first readout circuit coupled with the first readout terminal and configured to output a first readout voltage; a second readout circuit coupled with the second readout terminal and configured to output a second readout voltage; and a common-mode analog-to-digital converter (ADC) including: a first input terminal coupled with a first voltage source; a second input terminal coupled with a common-mode generator, the common-mode generator configured to receive the first readout voltage and the second readout voltage, and to generate a common-mode voltage between the first and second readout voltages; and a first output terminal configured to output a first output signal corresponding to a magnitude of a current generated by the photodetector.

A circuit, including: a photodetector including a first readout terminal and a second readout terminal different than the first readout terminal; a first readout circuit coupled with the first readout terminal and configured to output a first readout voltage; a second readout circuit coupled with the second readout terminal and configured to output a second readout voltage; and a common-mode analog-to-digital converter (ADC) including: a first input terminal coupled with a first voltage source; a second input terminal coupled with a common-mode generator, the common-mode generator configured to receive the first readout voltage and the second readout voltage, and to generate a common-mode voltage between the first and second readout voltages; and a first output terminal configured to output a first output signal corresponding to a magnitude of a current generated by the photodetector.

The present disclosure describes a semiconductor device and methods for forming the same. The semiconductor device includes nanostructures on a substrate and a source/drain region in contact with the nanostructures. The source/drain region includes epitaxial end caps, where each epitaxial end cap is formed at an end portion of a nanostructure of the nanostructures. The source/drain region also includes an epitaxial body in contact with the epitaxial end caps and an epitaxial top cap formed on the epitaxial body. The semiconductor device further includes gate structure formed on the nanostructures.

A semiconductor device includes a substrate including a first region, a second region, and active regions extending in a first direction in the first region and in the second region; gate electrodes on the first region and the second region, the gate electrodes intersecting the active regions and extending in a second direction; a plurality of channel layers spaced apart from each other in a third direction on active regions of the active regions and encompassed by the gate electrodes, the third direction being perpendicular to an upper surface of the substrate; and first source/drain regions and second source/drain regions in portions of the active regions that are recessed on both sides of the gate electrodes, the first source/drain regions and the second source/drain regions being connected to the plurality of channel layers, wherein the first source/drain regions are in the first region, and the second source/drain regions are in the second region, wherein an end portion of each of the first source/drain regions in the second direction in a plan view includes a tip region protruding in the second direction, and wherein an end portion of each of the second source/drain regions in the second direction in the plan view extends flatly in the first direction.

A semiconductor device includes a substrate including a first region, a second region, and active regions extending in a first direction in the first region and in the second region; gate electrodes on the first region and the second region, the gate electrodes intersecting the active regions and extending in a second direction; a plurality of channel layers spaced apart from each other in a third direction on active regions of the active regions and encompassed by the gate electrodes, the third direction being perpendicular to an upper surface of the substrate; and first source/drain regions and second source/drain regions in portions of the active regions that are recessed on both sides of the gate electrodes, the first source/drain regions and the second source/drain regions being connected to the plurality of channel layers, wherein the first source/drain regions are in the first region, and the second source/drain regions are in the second region, wherein an end portion of each of the first source/drain regions in the second direction in a plan view includes a tip region protruding in the second direction, and wherein an end portion of each of the second source/drain regions in the second direction in the plan view extends flatly in the first direction.

In a method of forming a semiconductor device, an epitaxial layer stack is formed over a substrate. The epitaxial layer stack includes intermediate layers, one or more first nano layers and one or more second nano layers positioned below the one or more first nano layers. Trenches are formed in the epitaxial layer stack to separate the epitaxial layer stack into sub-stacks, the one of more first nano layers into first nano-channels, and the one or more second nano layers into second nano-channels. The intermediate layers are recessed so that one or more first nano-channels of the first nano-channels and one or more second nano-channels of the second nano-channels in each of the sub-stacks protrude from sidewalls of the intermediate layers. Bottom source/drain (S/D) regions are formed in the trenches to connect the second nano-channels. Top S/D regions are formed in the trenches to connect the first nano-channels.

A device includes an isolation structure, a source/drain epi-layer, a contact, a first dielectric layer, and a second dielectric layer. The isolation structure is embedded in a substrate. The source/drain epi-layer is embedded in the substrate and is in contact with the isolation structure. The contact is over the source/drain epi-layer. The first dielectric layer wraps the contact. The second dielectric layer is between the contact and the first dielectric layer. The first and second dielectric layers include different materials, and a portion of the source/drain epi-layer is directly between a bottom portion of the second dielectric layer and a top portion of the isolation structure.

A device includes an isolation structure, a source/drain epi-layer, a contact, a first dielectric layer, and a second dielectric layer. The isolation structure is embedded in a substrate. The source/drain epi-layer is embedded in the substrate and is in contact with the isolation structure. The contact is over the source/drain epi-layer. The first dielectric layer wraps the contact. The second dielectric layer is between the contact and the first dielectric layer. The first and second dielectric layers include different materials, and a portion of the source/drain epi-layer is directly between a bottom portion of the second dielectric layer and a top portion of the isolation structure.

Source and drain contacts that provide improved contact resistance and contact interface stability for transistors employing silicon and germanium source and drain materials, related transistor structures, integrated circuits, systems, and methods of fabrication are disclosed. Such source and drain contacts include a contact layer of co-deposited titanium and silicon on the silicon and germanium source and drain. The disclosed source and drain contacts improve transistor performance including switching speed and reliability.