A high electron mobility transistor (HEMT) made of primarily nitride semiconductor materials is disclosed. The HEMT, which is a type of reverse HEMT, includes, on a C-polar surface of a SiC substrate, a barrier layer and a channel layer each having N-polar surfaces in respective top surfaces thereof. The HEMT further includes an intermediate layer highly doped with impurities and a Schottky barrier layer on the channel layer. The Schottky barrier layer and a portion of the intermediate layer are removed in portions beneath non-rectifying electrodes but a gate electrode is provided on the Schottky barrier layer.

The present disclosure provides a nitride semiconductor device. The nitride semiconductor device includes: an electron transport layer, made of a nitride semiconductor; an electron supply layer, disposed on the electron transport layer and made of a nitride semiconductor having a band gap greater than a band gap of the nitride semiconductor of the electron transport layer; a first protective layer, disposed on the electron supply layer and made of a nitride semiconductor having a band gap less than the band gap of the nitride semiconductor of the electron supply layer; a second protective layer, disposed on a portion of the first protective layer and made of a nitride semiconductor having a band gap greater than the band gap of the nitride semiconductor of the first protective layer; and a gate layer, disposed on the second protective layer.

The present disclosure is directed to controlling charge transfer in 2D materials. A charge-transfer controlled 2D device comprises a 2D active conducting material, a 2D charge transfer source material, and at least one overlapping portion wherein the 2D active conducting material overlaps the 2D charge transfer source material including at least one edge of the 2D charge transfer source material.

A semiconductor device includes a semiconductor stack, a third semiconductor structure, a dielectric layer, and a reflective layer under the third semiconductor structure. The semiconductor stack includes a first semiconductor structure, an active structure, a second semiconductor structure. The first semiconductor structure has a first surface which includes a first portion and a second portion, and the first surface has a first area. The third semiconductor structure connects to the first portion, and has a second surface with a second area. The dielectric layer connects to the second portion and includes a plurality of openings, and the plurality of openings have a third area. A ratio of the second area to the first area is between 0.1˜0.7, and a ratio of the third area to the first area is less than 0.2.

Embodiments relate to the field of semiconductor technology, and propose a semiconductor structure and a method for fabricating a semiconductor structure. The semiconductor structure includes: a channel layer including a group III-V semiconductor and a group III-V semiconductor layer, the group III-V semiconductor and the group III-V semiconductor layer forming a heterojunction; a gate structure positioned on the channel layer, the gate structure including a gallium oxide layer, a gate oxide layer, and a gate electrode stacked in sequence; a source electrode positioned at an end of the heterojunction; and a drain electrode positioned at other end of the heterojunction.

A method for manufacturing a semiconductor device includes preparing a first substrate provided with a first pattern on a first surface, and a semiconductor chip having a second surface, and a third surface opposite to the second surface, and including a second pattern provided on the second surface, recognizing the first pattern from a position near the first surface among the first surface and an opposite surface thereof in the first substrate, recognizing the second pattern by transmitting through the semiconductor chip from a position near the third surface among the second surface and the third surface in the semiconductor chip, aligning the semiconductor chip and the first substrate based on a recognition result of the first pattern and the second pattern, and bonding the semiconductor chip to the first substrate so that the second surface faces the first surface.

The present disclosure relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The structure includes: a gate structure comprising a horizontal portion and a substantially vertical stem portion; and an air gap surrounding the substantially vertical stem portion and having a curved surface under the horizontal portion.

A circuit includes a field effect transistor (FET), a reference transistor having an output coupled to an output of the FET, an active bias circuit coupled to the reference transistor and configured to generate an input signal for the reference transistor in response to a change in drain current of the reference transistor due to carrier trapping and to apply the input signal to an input of the reference transistor, and a summing node coupled to an input of the FET and to the input of the reference transistor. The summing node adds the input signal to an input signal of the FET to compensate the carrier trapping effect.

A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.

A high efficiency satellite transmitter comprises an RF amplifier chip in thermal contact with a radiant cooling element via a heat conducting element. The RF amplifier chip comprises an active layer disposed on a high thermal conductivity substrate having a thermal conductivity greater than about 1000 W/mK, maximizing heat conduction out of the RF amplifier chip and ultimately into outer space when the chip is operating within a satellite under normal transmission conditions. In one embodiment, the active layer comprises materials selected from the group consisting of GaN, InGaN, AlGaN, and InGaAlN alloys. In one embodiment, the high thermal conductivity substrate comprises synthetic diamond.